Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	72841653	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	74663866	1		T1	142796		T2	27302		T3	1140

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	145921313	1		T1	44546		T2	54347		T3	2254
values[0x0]	752665	1		T1	52776		T2	7		T3	5
values[0x1]	831541	1		T1	57945		T2	12		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58165073	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	89340446	1		T1	148336		T2	32698		T3	1353

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	438742	1		T1	635		T3	4		T4	6024
valid_sources[0x01]	2683353	1		T1	593		T3	14		T4	5943
valid_sources[0x02]	1725310	1		T1	610		T3	2		T4	5708
valid_sources[0x03]	439684	1		T1	584		T3	20		T4	6031
valid_sources[0x04]	438468	1		T1	636		T3	19		T4	6152
valid_sources[0x05]	440794	1		T1	611		T3	3		T4	6054
valid_sources[0x06]	443618	1		T1	592		T3	12		T4	6006
valid_sources[0x07]	919542	1		T1	599		T3	2		T4	5765
valid_sources[0x08]	440414	1		T1	627		T3	1		T4	5844
valid_sources[0x09]	438984	1		T1	545		T3	6		T4	5943
valid_sources[0x0a]	441765	1		T1	603		T3	7		T4	5806
valid_sources[0x0b]	439918	1		T1	576		T3	1		T4	6048
valid_sources[0x0c]	755989	1		T1	548		T3	17		T4	6161
valid_sources[0x0d]	855014	1		T1	569		T3	5		T4	6107
valid_sources[0x0e]	442360	1		T1	631		T3	13		T4	5864
valid_sources[0x0f]	436075	1		T1	634		T3	20		T4	5598
valid_sources[0x10]	440471	1		T1	640		T3	12		T4	5957
valid_sources[0x11]	442739	1		T1	576		T3	10		T4	5838
valid_sources[0x12]	442647	1		T1	579		T3	9		T4	6194
valid_sources[0x13]	437434	1		T1	613		T3	3		T4	6042
valid_sources[0x14]	436513	1		T1	593		T3	13		T4	5998
valid_sources[0x15]	437164	1		T1	619		T3	12		T4	5859
valid_sources[0x16]	435993	1		T1	586		T3	1		T4	5866
valid_sources[0x17]	438885	1		T1	570		T3	5		T4	6061
valid_sources[0x18]	436859	1		T1	592		T3	12		T4	5686
valid_sources[0x19]	439734	1		T1	574		T3	18		T4	5849
valid_sources[0x1a]	441260	1		T1	621		T3	2		T4	5817
valid_sources[0x1b]	448036	1		T1	607		T3	16		T4	6155
valid_sources[0x1c]	439329	1		T1	573		T3	7		T4	5989
valid_sources[0x1d]	3147951	1		T1	596		T4	5967		T8	425
valid_sources[0x1e]	446902	1		T1	594		T4	6031		T8	478
valid_sources[0x1f]	441948	1		T1	601		T3	6		T4	5934
valid_sources[0x20]	472894	1		T1	627		T3	1		T4	5913
valid_sources[0x21]	478023	1		T1	594		T3	11		T4	5890
valid_sources[0x22]	715072	1		T1	561		T4	5813		T8	464
valid_sources[0x23]	436811	1		T1	613		T3	6		T4	5981
valid_sources[0x24]	438650	1		T1	632		T3	10		T4	6165
valid_sources[0x25]	437273	1		T1	596		T3	5		T4	5936
valid_sources[0x26]	497040	1		T1	538		T3	14		T4	6016
valid_sources[0x27]	767242	1		T1	632		T3	20		T4	6096
valid_sources[0x28]	442110	1		T1	597		T3	19		T4	5960
valid_sources[0x29]	496665	1		T1	623		T3	18		T4	5892
valid_sources[0x2a]	437241	1		T1	612		T3	11		T4	5711
valid_sources[0x2b]	493932	1		T1	646		T2	54366		T3	8
valid_sources[0x2c]	500832	1		T1	608		T3	5		T4	5889
valid_sources[0x2d]	452004	1		T1	589		T3	5		T4	5975
valid_sources[0x2e]	450420	1		T1	596		T3	14		T4	5935
valid_sources[0x2f]	440037	1		T1	571		T4	6220		T8	440
valid_sources[0x30]	435986	1		T1	600		T3	15		T4	6004
valid_sources[0x31]	438328	1		T1	599		T3	2		T4	5917
valid_sources[0x32]	437840	1		T1	605		T3	22		T4	5828
valid_sources[0x33]	438593	1		T1	583		T3	7		T4	5871
valid_sources[0x34]	436649	1		T1	614		T3	3		T4	6017
valid_sources[0x35]	449549	1		T1	621		T3	6		T4	6014
valid_sources[0x36]	2904168	1		T1	624		T3	8		T4	5942
valid_sources[0x37]	437004	1		T1	528		T3	9		T4	6037
valid_sources[0x38]	436332	1		T1	620		T3	16		T4	5798
valid_sources[0x39]	438166	1		T1	592		T3	12		T4	5782
valid_sources[0x3a]	437633	1		T1	585		T3	10		T4	6003
valid_sources[0x3b]	437784	1		T1	576		T3	2		T4	5931
valid_sources[0x3c]	454082	1		T1	615		T3	10		T4	6260
valid_sources[0x3d]	438765	1		T1	643		T3	3		T4	5986
valid_sources[0x3e]	963429	1		T1	605		T3	3		T4	6160
valid_sources[0x3f]	437673	1		T1	625		T3	9		T4	5762
valid_sources[0x40]	538961	1		T1	631		T3	12		T4	6086
valid_sources[0x41]	516526	1		T1	624		T3	16		T4	6137
valid_sources[0x42]	2933392	1		T1	625		T3	12		T4	6157
valid_sources[0x43]	436579	1		T1	611		T3	15		T4	6023
valid_sources[0x44]	438200	1		T1	604		T3	7		T4	5791
valid_sources[0x45]	890808	1		T1	589		T3	8		T4	6047
valid_sources[0x46]	436903	1		T1	629		T3	13		T4	6095
valid_sources[0x47]	441225	1		T1	643		T3	11		T4	6036
valid_sources[0x48]	435172	1		T1	617		T3	16		T4	6147
valid_sources[0x49]	436545	1		T1	599		T3	22		T4	6056
valid_sources[0x4a]	440129	1		T1	642		T3	9		T4	5937
valid_sources[0x4b]	437649	1		T1	610		T3	7		T4	5843
valid_sources[0x4c]	438528	1		T1	648		T4	5875		T8	426
valid_sources[0x4d]	439971	1		T1	632		T3	5		T4	5924
valid_sources[0x4e]	615197	1		T1	595		T3	14		T4	6196
valid_sources[0x4f]	438796	1		T1	631		T3	24		T4	5989
valid_sources[0x50]	438437	1		T1	591		T3	7		T4	6153
valid_sources[0x51]	436875	1		T1	560		T3	6		T4	5639
valid_sources[0x52]	444761	1		T1	607		T3	1		T4	6068
valid_sources[0x53]	434721	1		T1	641		T3	13		T4	5956
valid_sources[0x54]	438410	1		T1	658		T4	5921		T8	487
valid_sources[0x55]	463823	1		T1	633		T3	12		T4	6104
valid_sources[0x56]	436590	1		T1	563		T3	5		T4	5779
valid_sources[0x57]	443506	1		T1	621		T3	17		T4	6245
valid_sources[0x58]	441039	1		T1	604		T3	7		T4	5939
valid_sources[0x59]	440572	1		T1	606		T3	4		T4	6308
valid_sources[0x5a]	438947	1		T1	594		T3	18		T4	5871
valid_sources[0x5b]	886865	1		T1	585		T3	10		T4	6006
valid_sources[0x5c]	438048	1		T1	600		T3	4		T4	6096
valid_sources[0x5d]	440572	1		T1	577		T3	11		T4	5797
valid_sources[0x5e]	447805	1		T1	641		T3	6		T4	5770
valid_sources[0x5f]	457655	1		T1	623		T3	1		T4	5909
valid_sources[0x60]	439987	1		T1	585		T3	3		T4	6090
valid_sources[0x61]	436237	1		T1	635		T3	5		T4	5923
valid_sources[0x62]	436080	1		T1	575		T3	26		T4	6221
valid_sources[0x63]	439893	1		T1	590		T3	7		T4	5912
valid_sources[0x64]	439337	1		T1	612		T3	8		T4	6168
valid_sources[0x65]	515360	1		T1	576		T3	10		T4	6272
valid_sources[0x66]	460877	1		T1	583		T3	5		T4	6010
valid_sources[0x67]	437731	1		T1	595		T3	6		T4	6126
valid_sources[0x68]	966274	1		T1	621		T4	6123		T6	1
valid_sources[0x69]	440999	1		T1	649		T3	8		T4	6131
valid_sources[0x6a]	438732	1		T1	613		T3	11		T4	5878
valid_sources[0x6b]	774165	1		T1	630		T3	1		T4	5866
valid_sources[0x6c]	563885	1		T1	586		T3	15		T4	5785
valid_sources[0x6d]	1018947	1		T1	614		T3	2		T4	6309
valid_sources[0x6e]	439385	1		T1	617		T3	7		T4	6000
valid_sources[0x6f]	438301	1		T1	566		T3	9		T4	5714
valid_sources[0x70]	439962	1		T1	634		T3	3		T4	6096
valid_sources[0x71]	436798	1		T1	615		T3	8		T4	5987
valid_sources[0x72]	489667	1		T1	589		T3	10		T4	5988
valid_sources[0x73]	434505	1		T1	647		T3	2		T4	5750
valid_sources[0x74]	439298	1		T1	597		T3	21		T4	6301
valid_sources[0x75]	467747	1		T1	616		T3	14		T4	5927
valid_sources[0x76]	1279569	1		T1	588		T3	9		T4	5576
valid_sources[0x77]	3068006	1		T1	628		T3	1		T4	5749
valid_sources[0x78]	439046	1		T1	591		T3	5		T4	5971
valid_sources[0x79]	437519	1		T1	559		T3	3		T4	6148
valid_sources[0x7a]	465259	1		T1	625		T3	9		T4	6144
valid_sources[0x7b]	441318	1		T1	596		T3	4		T4	6115
valid_sources[0x7c]	1249939	1		T1	617		T3	6		T4	6031
valid_sources[0x7d]	438457	1		T1	558		T3	7		T4	6161
valid_sources[0x7e]	438113	1		T1	550		T3	25		T4	5924
valid_sources[0x7f]	841797	1		T1	612		T3	26		T4	6260
valid_sources[0x80]	439883	1		T1	643		T3	1		T4	6047

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73185637

1

T1

38690

T2

27292

T3

1130

values[0x0]

all_enables

biggest_size

739556

1

T1

52165

T2

4

T3

4

values[0x1]

all_enables

biggest_size

738673

1

T1

51941

T2

6

T3

6