Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2571299	0	0
cfg0_rd_A	2147483647	5757	0	0
compare_lower0_0_rd_A	2147483647	5880	0	0
compare_upper0_0_rd_A	2147483647	5309	0	0
ctrl_rd_A	2147483647	5308	0	0
intr_enable0_rd_A	2147483647	6874	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2571299	0	0
T1	427171	178824	0	0
T2	784987	0	0	0
T3	423267	0	0	0
T4	116526	0	0	0
T5	135194	0	0	0
T6	22534	0	0	0
T7	752350	0	0	0
T8	124113	0	0	0
T9	156545	0	0	0
T10	221125	0	0	0
T12	0	82920	0	0
T13	0	258343	0	0
T35	0	131202	0	0
T36	0	70021	0	0
T37	0	52115	0	0
T38	0	324227	0	0
T39	0	94403	0	0
T40	0	367043	0	0
T41	0	370044	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5757	0	0
T29	0	34	0	0
T37	535735	530	0	0
T42	0	1162	0	0
T43	0	904	0	0
T44	0	978	0	0
T45	0	28	0	0
T46	0	35	0	0
T47	0	686	0	0
T48	0	195	0	0
T49	0	3	0	0
T50	548932	0	0	0
T51	495128	0	0	0
T52	145705	0	0	0
T53	147330	0	0	0
T54	261855	0	0	0
T55	368448	0	0	0
T56	813670	0	0	0
T57	3172	0	0	0
T58	149293	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5880	0	0
T29	0	13	0	0
T37	535735	629	0	0
T42	0	1274	0	0
T43	0	880	0	0
T44	0	1245	0	0
T45	0	17	0	0
T46	0	29	0	0
T47	0	628	0	0
T48	0	127	0	0
T50	548932	0	0	0
T51	495128	0	0	0
T52	145705	0	0	0
T53	147330	0	0	0
T54	261855	0	0	0
T55	368448	0	0	0
T56	813670	0	0	0
T57	3172	0	0	0
T58	149293	0	0	0
T59	0	16	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5309	0	0
T29	0	29	0	0
T37	535735	479	0	0
T42	0	1112	0	0
T43	0	717	0	0
T44	0	1110	0	0
T45	0	10	0	0
T46	0	33	0	0
T47	0	699	0	0
T48	0	100	0	0
T50	548932	0	0	0
T51	495128	0	0	0
T52	145705	0	0	0
T53	147330	0	0	0
T54	261855	0	0	0
T55	368448	0	0	0
T56	813670	0	0	0
T57	3172	0	0	0
T58	149293	0	0	0
T59	0	3	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5308	0	0
T29	0	23	0	0
T37	535735	484	0	0
T42	0	1191	0	0
T43	0	739	0	0
T44	0	1096	0	0
T45	0	7	0	0
T46	0	33	0	0
T47	0	628	0	0
T48	0	109	0	0
T50	548932	0	0	0
T51	495128	0	0	0
T52	145705	0	0	0
T53	147330	0	0	0
T54	261855	0	0	0
T55	368448	0	0	0
T56	813670	0	0	0
T57	3172	0	0	0
T58	149293	0	0	0
T60	0	11	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6874	0	0
T10	221125	32	0	0
T11	117134	0	0	0
T34	505596	0	0	0
T37	0	713	0	0
T42	0	1286	0	0
T57	0	59	0	0
T61	0	73	0	0
T62	0	15	0	0
T63	0	23	0	0
T64	0	95	0	0
T65	0	16	0	0
T66	0	14	0	0
T67	109479	0	0	0
T68	683927	0	0	0
T69	103869	0	0	0
T70	112607	0	0	0
T71	942210	0	0	0
T72	956675	0	0	0
T73	901765	0	0	0