Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2100846	0	0
cfg0_rd_A	2147483647	5946	0	0
compare_lower0_0_rd_A	2147483647	6117	0	0
compare_upper0_0_rd_A	2147483647	5604	0	0
ctrl_rd_A	2147483647	5654	0	0
intr_enable0_rd_A	2147483647	7093	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2100846	0	0
T2	103218	41057	0	0
T3	107735	0	0	0
T4	175000	0	0	0
T5	6023	0	0	0
T6	134014	0	0	0
T7	680648	0	0	0
T8	172623	0	0	0
T9	595218	0	0	0
T10	213488	0	0	0
T13	0	98572	0	0
T14	0	36408	0	0
T19	554191	0	0	0
T28	0	242463	0	0
T29	0	87075	0	0
T30	0	108738	0	0
T31	0	225825	0	0
T32	0	23022	0	0
T33	0	84271	0	0
T34	0	242055	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5946	0	0
T25	0	12	0	0
T31	853906	2500	0	0
T32	899918	237	0	0
T33	277946	0	0	0
T35	0	1059	0	0
T36	0	16	0	0
T37	0	4	0	0
T38	0	37	0	0
T39	0	40	0	0
T40	0	18	0	0
T41	0	77	0	0
T42	376034	0	0	0
T43	516821	0	0	0
T44	118357	0	0	0
T45	521112	0	0	0
T46	184511	0	0	0
T47	129103	0	0	0
T48	787604	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6117	0	0
T25	0	12	0	0
T31	853906	2667	0	0
T32	899918	284	0	0
T33	277946	0	0	0
T35	0	1153	0	0
T36	0	4	0	0
T37	0	9	0	0
T38	0	23	0	0
T39	0	19	0	0
T40	0	16	0	0
T42	376034	0	0	0
T43	516821	0	0	0
T44	118357	0	0	0
T45	521112	0	0	0
T46	184511	0	0	0
T47	129103	0	0	0
T48	787604	0	0	0
T49	0	7	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5604	0	0
T25	0	13	0	0
T31	853906	2258	0	0
T32	899918	280	0	0
T33	277946	0	0	0
T35	0	1158	0	0
T36	0	10	0	0
T37	0	6	0	0
T38	0	24	0	0
T39	0	9	0	0
T40	0	19	0	0
T42	376034	0	0	0
T43	516821	0	0	0
T44	118357	0	0	0
T45	521112	0	0	0
T46	184511	0	0	0
T47	129103	0	0	0
T48	787604	0	0	0
T49	0	10	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5654	0	0
T25	0	15	0	0
T31	853906	2154	0	0
T32	899918	236	0	0
T33	277946	0	0	0
T35	0	1198	0	0
T36	0	23	0	0
T37	0	18	0	0
T38	0	23	0	0
T39	0	25	0	0
T40	0	12	0	0
T41	0	53	0	0
T42	376034	0	0	0
T43	516821	0	0	0
T44	118357	0	0	0
T45	521112	0	0	0
T46	184511	0	0	0
T47	129103	0	0	0
T48	787604	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7093	0	0
T4	175000	32	0	0
T5	6023	0	0	0
T6	134014	0	0	0
T7	680648	0	0	0
T8	172623	0	0	0
T9	595218	0	0	0
T10	213488	0	0	0
T11	335416	0	0	0
T19	554191	0	0	0
T20	556176	0	0	0
T50	0	64	0	0
T51	0	40	0	0
T52	0	18	0	0
T53	0	31	0	0
T54	0	45	0	0
T55	0	6	0	0
T56	0	9	0	0
T57	0	13	0	0
T58	0	61	0	0