Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61154257	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	61909323	1		T1	8		T2	411		T3	17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	122408637	1		T1	11		T2	808		T3	22
values[0x0]	312112	1		T1	5		T2	3		T3	11
values[0x1]	342831	1		T1	5		T2	4		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48859777	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	74203803	1		T1	9		T2	493		T3	22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	357706	1		T2	2		T4	2134		T7	45
valid_sources[0x01]	678835	1		T2	3		T4	2219		T7	40
valid_sources[0x02]	356407	1		T2	4		T4	2121		T7	20
valid_sources[0x03]	377990	1		T4	2130		T7	18		T9	88
valid_sources[0x04]	357663	1		T2	3		T4	2446		T7	34
valid_sources[0x05]	610956	1		T2	1		T4	2316		T7	46
valid_sources[0x06]	358703	1		T2	3		T4	2155		T7	38
valid_sources[0x07]	357282	1		T2	5		T4	2354		T7	42
valid_sources[0x08]	471234	1		T2	1		T4	2168		T7	19
valid_sources[0x09]	356475	1		T2	1		T4	2359		T7	34
valid_sources[0x0a]	364537	1		T2	1		T4	2157		T7	21
valid_sources[0x0b]	358119	1		T2	2		T4	2369		T7	58
valid_sources[0x0c]	355890	1		T2	4		T4	2228		T7	41
valid_sources[0x0d]	396034	1		T2	7		T4	2507		T7	35
valid_sources[0x0e]	484936	1		T2	3		T4	2154		T7	32
valid_sources[0x0f]	353668	1		T2	3		T4	2121		T7	41
valid_sources[0x10]	359128	1		T2	3		T4	2245		T7	38
valid_sources[0x11]	358018	1		T2	5		T4	2220		T7	13
valid_sources[0x12]	357365	1		T2	1		T4	2156		T7	16
valid_sources[0x13]	364852	1		T2	1		T4	2127		T7	23
valid_sources[0x14]	358719	1		T2	2		T4	2045		T7	40
valid_sources[0x15]	356801	1		T2	1		T4	2138		T7	10
valid_sources[0x16]	357894	1		T2	6		T4	2377		T7	28
valid_sources[0x17]	601779	1		T2	4		T4	2369		T7	14
valid_sources[0x18]	381190	1		T2	1		T4	2145		T7	46
valid_sources[0x19]	921486	1		T2	2		T4	2326		T7	39
valid_sources[0x1a]	734189	1		T3	2		T4	2530		T7	54
valid_sources[0x1b]	488951	1		T2	6		T4	2107		T7	50
valid_sources[0x1c]	359058	1		T2	8		T4	2285		T7	33
valid_sources[0x1d]	355607	1		T4	2294		T7	47		T9	112
valid_sources[0x1e]	358829	1		T2	7		T4	2403		T7	38
valid_sources[0x1f]	357113	1		T2	2		T4	2089		T7	25
valid_sources[0x20]	354622	1		T2	2		T4	2327		T7	28
valid_sources[0x21]	358101	1		T2	5		T4	2125		T7	33
valid_sources[0x22]	359035	1		T2	1		T4	2266		T7	40
valid_sources[0x23]	486516	1		T2	5		T4	2252		T5	29451
valid_sources[0x24]	704324	1		T2	1		T4	2130		T7	19
valid_sources[0x25]	355803	1		T2	4		T4	2178		T7	39
valid_sources[0x26]	359917	1		T2	8		T4	2194		T7	62
valid_sources[0x27]	417093	1		T2	3		T4	2286		T7	26
valid_sources[0x28]	358748	1		T2	2		T4	2227		T7	39
valid_sources[0x29]	818735	1		T2	5		T4	2110		T7	24
valid_sources[0x2a]	353275	1		T2	1		T4	2179		T7	13
valid_sources[0x2b]	355696	1		T2	1		T4	2090		T7	36
valid_sources[0x2c]	357151	1		T2	2		T4	2225		T7	30
valid_sources[0x2d]	361855	1		T2	10		T3	1		T4	2235
valid_sources[0x2e]	358699	1		T2	3		T4	2245		T7	46
valid_sources[0x2f]	358434	1		T2	5		T4	2180		T7	26
valid_sources[0x30]	359300	1		T2	3		T4	2151		T7	63
valid_sources[0x31]	360097	1		T2	3		T4	2271		T7	51
valid_sources[0x32]	382829	1		T2	2		T4	2347		T7	41
valid_sources[0x33]	568466	1		T2	6		T4	2365		T7	29
valid_sources[0x34]	774318	1		T2	5		T4	2296		T7	22
valid_sources[0x35]	356493	1		T2	3		T4	2155		T7	20
valid_sources[0x36]	359184	1		T2	3		T4	2145		T7	43
valid_sources[0x37]	361095	1		T2	1		T3	1		T4	2221
valid_sources[0x38]	357143	1		T2	1		T4	2312		T7	34
valid_sources[0x39]	357233	1		T2	1		T4	2088		T7	57
valid_sources[0x3a]	359980	1		T2	2		T4	2344		T7	5
valid_sources[0x3b]	356662	1		T2	2		T4	2359		T7	36
valid_sources[0x3c]	356417	1		T2	8		T4	2268		T7	26
valid_sources[0x3d]	2835420	1		T2	2		T4	2308		T7	18
valid_sources[0x3e]	448414	1		T2	4		T4	2189		T7	16
valid_sources[0x3f]	358758	1		T2	3		T4	2208		T7	31
valid_sources[0x40]	356418	1		T4	2247		T7	32		T9	133
valid_sources[0x41]	520981	1		T2	2		T4	2244		T6	52457
valid_sources[0x42]	356832	1		T2	3		T4	2106		T7	18
valid_sources[0x43]	355979	1		T2	1		T4	2098		T7	25
valid_sources[0x44]	355969	1		T2	2		T4	2240		T7	48
valid_sources[0x45]	354286	1		T2	1		T4	2228		T7	65
valid_sources[0x46]	755749	1		T2	3		T4	2207		T7	15
valid_sources[0x47]	357279	1		T2	2		T4	2253		T7	40
valid_sources[0x48]	357746	1		T2	2		T4	2248		T7	35
valid_sources[0x49]	358801	1		T2	6		T4	2239		T7	20
valid_sources[0x4a]	362108	1		T2	4		T4	2146		T7	24
valid_sources[0x4b]	389186	1		T2	3		T4	2327		T7	26
valid_sources[0x4c]	744957	1		T2	2		T4	2256		T7	56
valid_sources[0x4d]	357455	1		T2	4		T4	2280		T7	22
valid_sources[0x4e]	356524	1		T2	5		T4	2123		T7	37
valid_sources[0x4f]	355799	1		T2	4		T4	2255		T7	21
valid_sources[0x50]	1386809	1		T2	2		T4	2128		T7	18
valid_sources[0x51]	356751	1		T2	7		T4	2443		T7	29
valid_sources[0x52]	365273	1		T2	9		T4	2349		T7	29
valid_sources[0x53]	357599	1		T2	1		T4	2146		T7	20
valid_sources[0x54]	355722	1		T2	1		T3	1		T4	2081
valid_sources[0x55]	2110515	1		T2	1		T4	2212		T7	29
valid_sources[0x56]	400405	1		T2	8		T4	2208		T7	17
valid_sources[0x57]	356632	1		T2	4		T4	2262		T7	23
valid_sources[0x58]	355603	1		T2	4		T4	2111		T7	24
valid_sources[0x59]	359279	1		T2	3		T4	2058		T7	37
valid_sources[0x5a]	752028	1		T2	2		T4	2192		T7	25
valid_sources[0x5b]	357425	1		T2	1		T4	2394		T7	18
valid_sources[0x5c]	356152	1		T2	1		T4	2191		T7	34
valid_sources[0x5d]	373122	1		T2	5		T4	2165		T7	24
valid_sources[0x5e]	357256	1		T2	2		T4	2190		T7	34
valid_sources[0x5f]	489057	1		T4	2180		T7	29		T9	94
valid_sources[0x60]	358017	1		T2	1		T4	2324		T7	24
valid_sources[0x61]	1737373	1		T2	4		T3	3		T4	2244
valid_sources[0x62]	355869	1		T2	4		T4	2229		T7	29
valid_sources[0x63]	357100	1		T4	2173		T7	45		T9	99
valid_sources[0x64]	1218027	1		T2	2		T4	2318		T7	50
valid_sources[0x65]	360617	1		T2	10		T4	2359		T7	38
valid_sources[0x66]	860715	1		T2	1		T4	2371		T7	42
valid_sources[0x67]	357888	1		T2	2		T4	2208		T7	47
valid_sources[0x68]	358952	1		T2	2		T4	2460		T7	50
valid_sources[0x69]	358223	1		T2	6		T4	2180		T7	50
valid_sources[0x6a]	1995352	1		T2	3		T4	2344		T7	36
valid_sources[0x6b]	359055	1		T4	2201		T7	27		T9	86
valid_sources[0x6c]	356535	1		T2	1		T3	4		T4	2070
valid_sources[0x6d]	849611	1		T2	3		T4	1985		T7	24
valid_sources[0x6e]	359185	1		T2	5		T4	2158		T7	41
valid_sources[0x6f]	376726	1		T2	3		T4	2371		T7	49
valid_sources[0x70]	358862	1		T4	2141		T7	23		T9	119
valid_sources[0x71]	357153	1		T2	5		T4	2119		T7	23
valid_sources[0x72]	357053	1		T2	6		T4	2286		T7	47
valid_sources[0x73]	359842	1		T2	5		T3	2		T4	2255
valid_sources[0x74]	359104	1		T2	1		T4	2089		T7	37
valid_sources[0x75]	358446	1		T2	5		T4	2177		T7	36
valid_sources[0x76]	354529	1		T2	1		T4	2227		T7	28
valid_sources[0x77]	356837	1		T2	2		T4	2060		T7	31
valid_sources[0x78]	392824	1		T2	7		T4	2206		T7	54
valid_sources[0x79]	371361	1		T2	10		T4	2238		T7	37
valid_sources[0x7a]	367016	1		T2	1		T4	2330		T7	24
valid_sources[0x7b]	357500	1		T2	3		T4	2195		T7	32
valid_sources[0x7c]	361672	1		T2	3		T4	2412		T7	16
valid_sources[0x7d]	356855	1		T2	3		T4	2328		T7	42
valid_sources[0x7e]	355362	1		T2	5		T4	2208		T7	45
valid_sources[0x7f]	357629	1		T2	3		T4	2168		T7	23
valid_sources[0x80]	357895	1		T2	5		T4	2034		T7	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61302882

1

T1

6

T2

406

T3

9

values[0x0]

all_enables

biggest_size

304062

1

T1

1

T2

2

T3

4

values[0x1]

all_enables

biggest_size

302379

1

T1

1

T2

3

T3

4