Unified Coverage Report :: Module :: rv_timer_reg_top

Module : rv_timer_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.71	99.24	99.29	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_cfg0_prescale	100.00	100.00	100.00			100.00
u_cfg0_step	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_compare_lower0_0	100.00	100.00	100.00			100.00
u_compare_lower0_00_qe	100.00	100.00				100.00
u_compare_upper0_0	100.00	100.00	100.00			100.00
u_compare_upper0_00_qe	100.00	100.00				100.00
u_ctrl	100.00	100.00	100.00			100.00
u_intr_enable0	100.00	100.00	100.00			100.00
u_intr_state0	100.00	100.00	100.00			100.00
u_intr_test0	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_timer_v_lower0	100.00	100.00	100.00			100.00
u_timer_v_upper0	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_timer_reg_top

	Line No.	Total	Covered	Percent
TOTAL		75	75	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
ALWAYS	479	11	11	100.00
CONT_ASSIGN	492	1	1	100.00
ALWAYS	496	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	516	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
ALWAYS	545	11	11	100.00
ALWAYS	560	13	13	100.00
CONT_ASSIGN	614	0	0
CONT_ASSIGN	622	1	1	100.00
CONT_ASSIGN	623	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
159	1	1
173	1	1
267	1	1
281	1	1
433	1	1
473	1	1
479	1	1
480	1	1
481	1	1
482	1	1
483	1	1
484	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
492	1	1
496	1	1
510	1	1
512	1	1
513	1	1
515	1	1
516	1	1
518	1	1
519	1	1
521	1	1
522	1	1
524	1	1
525	1	1
527	1	1
529	1	1
530	1	1
532	1	1
533	1	1
535	1	1
536	1	1
538	1	1
539	1	1
541	1	1
545	1	1
546	1	1
547	1	1
548	1	1
549	1	1
550	1	1
551	1	1
552	1	1
553	1	1
554	1	1
555	1	1
560	1	1
561	1	1
563	1	1
567	1	1
571	1	1
575	1	1
579	1	1
583	1	1
584	1	1
588	1	1
592	1	1
596	1	1
600	1	1
614		unreachable
622	1	1
623	1	1

---

Cond Coverage for Module : rv_timer_reg_top

	Total	Covered	Percent
Conditions	123	123	100.00
Logical	123	123	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T13,T14
1	1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T29,T30,T31

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T15,T16,T17
0	1	0	Covered	T29,T30,T31
1	0	0	Covered	T15,T16,T17

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T29,T30,T31
0	1	0	Covered	T12,T13,T14
1	0	0	Covered	T12,T13,T14

 LINE       480
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_ALERT_TEST_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T10,T11

 LINE       481
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_CTRL_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       482
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_INTR_ENABLE0_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       483
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_INTR_STATE0_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       484
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_INTR_TEST0_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       485
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_CFG0_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       486
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_TIMER_V_LOWER0_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       487
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_TIMER_V_UPPER0_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       488
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_COMPARE_LOWER0_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       489
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_COMPARE_UPPER0_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       492
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       492
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       496
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T13,T14

 LINE       496
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	Status	Tests
0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	0	0	0	1	Covered	T8,T10,T11
0	0	0	0	0	0	0	0	1	0	Covered	T8,T10,T11
0	0	0	0	0	0	0	1	0	0	Covered	T2,T4,T6
0	0	0	0	0	0	1	0	0	0	Covered	T2,T4,T6
0	0	0	0	0	1	0	0	0	0	Covered	T8,T10,T11
0	0	0	0	1	0	0	0	0	0	Covered	T1,T3,T4
0	0	0	1	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	1	0	0	0	0	0	0	0	Covered	T1,T3,T4
0	1	0	0	0	0	0	0	0	0	Covered	T8,T10,T11
1	0	0	0	0	0	0	0	0	0	Covered	T8,T10,T11

 LINE       496
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T10,T11
1	1	Covered	T8,T10,T11

 LINE       496
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T8,T10,T11

 LINE       496
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       496
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       496
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       496
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T8,T10,T11

 LINE       496
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T6

 LINE       496
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T6

 LINE       496
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T8,T10,T11

 LINE       496
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T8,T10,T11

 LINE       510
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T8,T10,T11
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T29,T32,T33

 LINE       513
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T2,T4,T5

 LINE       516
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T1,T2,T3

 LINE       519
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T1,T3,T4

 LINE       522
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T1,T3,T4

 LINE       525
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T2,T4,T5

 LINE       530
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T2,T4,T5

 LINE       533
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T2,T4,T5

 LINE       536
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T2,T4,T5

 LINE       539
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T12,T13,T14
1	1	1	Covered	T2,T4,T5

---

Branch Coverage for Module : rv_timer_reg_top

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
TERNARY	492	2	2	100.00
IF	68	3	3	100.00
CASE	561	11	11	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	492	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	561	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_timer_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	122281580	0	0
reAfterRv	2147483647	122281575	0	0
rePulse	2147483647	122213987	0	0
wePulse	2147483647	67588	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	122281580	0	0
T1	1742	21	0	0
T2	127460	815	0	0
T3	2428	43	0	0
T4	519731	570024	0	0
T5	112367	29451	0	0
T6	365892	52457	0	0
T7	127933	8334	0	0
T8	926987	42641	0	0
T9	103867	28999	0	0
T10	143341	29805	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	122281575	0	0
T1	1742	21	0	0
T2	127460	815	0	0
T3	2428	43	0	0
T4	519731	570024	0	0
T5	112367	29451	0	0
T6	365892	52457	0	0
T7	127933	8334	0	0
T8	926987	42641	0	0
T9	103867	28999	0	0
T10	143341	29805	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	122213987	0	0
T1	1742	11	0	0
T2	127460	808	0	0
T3	2428	22	0	0
T4	519731	569792	0	0
T5	112367	29411	0	0
T6	365892	52304	0	0
T7	127933	8299	0	0
T8	926987	42601	0	0
T9	103867	28940	0	0
T10	143341	29766	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	67588	0	0
T1	1742	10	0	0
T2	127460	7	0	0
T3	2428	21	0	0
T4	519731	232	0	0
T5	112367	40	0	0
T6	365892	153	0	0
T7	127933	35	0	0
T8	926987	40	0	0
T9	103867	59	0	0
T10	143341	39	0	0