Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1028547	0	0
cfg0_rd_A	2147483647	5133	0	0
compare_lower0_0_rd_A	2147483647	5332	0	0
compare_upper0_0_rd_A	2147483647	4923	0	0
ctrl_rd_A	2147483647	4653	0	0
intr_enable0_rd_A	2147483647	6353	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1028547	0	0
T12	431084	61833	0	0
T13	0	162276	0	0
T14	0	208370	0	0
T29	0	10	0	0
T34	0	43584	0	0
T35	0	79353	0	0
T36	0	208917	0	0
T37	0	114956	0	0
T38	0	134663	0	0
T39	0	793	0	0
T40	118125	0	0	0
T41	816562	0	0	0
T42	776387	0	0	0
T43	178425	0	0	0
T44	869809	0	0	0
T45	758919	0	0	0
T46	967	0	0	0
T47	590312	0	0	0
T48	402577	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5133	0	0
T12	431084	325	0	0
T13	0	1609	0	0
T14	0	2003	0	0
T29	0	103	0	0
T33	0	2	0	0
T39	0	25	0	0
T40	118125	0	0	0
T41	816562	0	0	0
T42	776387	0	0	0
T43	178425	0	0	0
T44	869809	0	0	0
T45	758919	0	0	0
T46	967	0	0	0
T47	590312	0	0	0
T48	402577	0	0	0
T49	0	3	0	0
T50	0	76	0	0
T51	0	29	0	0
T52	0	16	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5332	0	0
T12	431084	340	0	0
T13	0	1827	0	0
T14	0	2261	0	0
T29	0	62	0	0
T33	0	13	0	0
T39	0	12	0	0
T40	118125	0	0	0
T41	816562	0	0	0
T42	776387	0	0	0
T43	178425	0	0	0
T44	869809	0	0	0
T45	758919	0	0	0
T46	967	0	0	0
T47	590312	0	0	0
T48	402577	0	0	0
T49	0	7	0	0
T50	0	54	0	0
T51	0	14	0	0
T52	0	24	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4923	0	0
T12	431084	370	0	0
T13	0	1626	0	0
T14	0	1996	0	0
T29	0	85	0	0
T33	0	1	0	0
T39	0	14	0	0
T40	118125	0	0	0
T41	816562	0	0	0
T42	776387	0	0	0
T43	178425	0	0	0
T44	869809	0	0	0
T45	758919	0	0	0
T46	967	0	0	0
T47	590312	0	0	0
T48	402577	0	0	0
T49	0	12	0	0
T50	0	32	0	0
T51	0	15	0	0
T52	0	16	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4653	0	0
T12	431084	299	0	0
T13	0	1556	0	0
T14	0	2022	0	0
T29	0	45	0	0
T31	0	29	0	0
T39	0	8	0	0
T40	118125	0	0	0
T41	816562	0	0	0
T42	776387	0	0	0
T43	178425	0	0	0
T44	869809	0	0	0
T45	758919	0	0	0
T46	967	0	0	0
T47	590312	0	0	0
T48	402577	0	0	0
T49	0	3	0	0
T50	0	18	0	0
T51	0	23	0	0
T52	0	12	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6353	0	0
T1	1742	12	0	0
T2	127460	0	0	0
T3	2428	23	0	0
T4	519731	0	0	0
T5	112367	0	0	0
T6	365892	0	0	0
T7	127933	0	0	0
T8	926987	0	0	0
T9	103867	0	0	0
T10	143341	0	0	0
T12	0	435	0	0
T13	0	1819	0	0
T14	0	2652	0	0
T21	0	41	0	0
T53	0	26	0	0
T54	0	81	0	0
T55	0	9	0	0
T56	0	5	0	0