Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1311641	0	0
cfg0_rd_A	2147483647	3179	0	0
compare_lower0_0_rd_A	2147483647	3309	0	0
compare_upper0_0_rd_A	2147483647	3047	0	0
ctrl_rd_A	2147483647	3079	0	0
intr_enable0_rd_A	2147483647	4324	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1311641	0	0
T6	637328	200092	0	0
T7	783253	0	0	0
T8	426877	0	0	0
T9	898986	0	0	0
T10	130310	0	0	0
T11	196394	0	0	0
T12	0	80411	0	0
T13	0	35049	0	0
T33	0	25632	0	0
T34	0	48617	0	0
T35	0	130293	0	0
T36	0	115581	0	0
T37	0	75295	0	0
T38	0	261022	0	0
T39	0	326106	0	0
T40	175820	0	0	0
T41	889883	0	0	0
T42	102141	0	0	0
T43	402657	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3179	0	0
T33	108472	202	0	0
T36	0	655	0	0
T37	0	745	0	0
T44	0	106	0	0
T45	0	20	0	0
T46	0	136	0	0
T47	0	9	0	0
T48	0	420	0	0
T49	0	77	0	0
T50	0	12	0	0
T51	210255	0	0	0
T52	367088	0	0	0
T53	633625	0	0	0
T54	91720	0	0	0
T55	328113	0	0	0
T56	199339	0	0	0
T57	2175	0	0	0
T58	111598	0	0	0
T59	979357	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3309	0	0
T33	108472	310	0	0
T36	0	652	0	0
T37	0	926	0	0
T44	0	108	0	0
T45	0	6	0	0
T46	0	63	0	0
T47	0	1	0	0
T48	0	502	0	0
T49	0	79	0	0
T51	210255	0	0	0
T52	367088	0	0	0
T53	633625	0	0	0
T54	91720	0	0	0
T55	328113	0	0	0
T56	199339	0	0	0
T57	2175	0	0	0
T58	111598	0	0	0
T59	979357	0	0	0
T60	0	14	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3047	0	0
T33	108472	297	0	0
T36	0	501	0	0
T37	0	769	0	0
T44	0	121	0	0
T46	0	98	0	0
T47	0	21	0	0
T48	0	495	0	0
T49	0	49	0	0
T51	210255	0	0	0
T52	367088	0	0	0
T53	633625	0	0	0
T54	91720	0	0	0
T55	328113	0	0	0
T56	199339	0	0	0
T57	2175	0	0	0
T58	111598	0	0	0
T59	979357	0	0	0
T60	0	25	0	0
T61	0	3	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3079	0	0
T33	108472	261	0	0
T36	0	543	0	0
T37	0	802	0	0
T44	0	145	0	0
T45	0	9	0	0
T46	0	75	0	0
T47	0	4	0	0
T48	0	456	0	0
T49	0	62	0	0
T50	0	13	0	0
T51	210255	0	0	0
T52	367088	0	0	0
T53	633625	0	0	0
T54	91720	0	0	0
T55	328113	0	0	0
T56	199339	0	0	0
T57	2175	0	0	0
T58	111598	0	0	0
T59	979357	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4324	0	0
T14	8351	0	0	0
T19	109262	0	0	0
T20	143306	0	0	0
T21	841308	0	0	0
T22	416616	0	0	0
T23	320232	0	0	0
T24	847170	0	0	0
T25	126835	0	0	0
T33	0	356	0	0
T62	417611	34	0	0
T63	0	35	0	0
T64	0	36	0	0
T65	0	72	0	0
T66	0	59	0	0
T67	0	111	0	0
T68	0	67	0	0
T69	0	27	0	0
T70	0	77	0	0
T71	609469	0	0	0