Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62040797	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	63063130	1		T1	11396		T2	4192		T3	47806

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	124216857	1		T1	22578		T2	8278		T3	95465
values[0x0]	421365	1		T1	70		T2	19		T3	9
values[0x1]	465705	1		T1	101		T2	25		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49551896	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	75552031	1		T1	13700		T2	5063		T3	57579

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	852578	1		T1	87		T3	519		T4	89
valid_sources[0x01]	390390	1		T1	103		T3	467		T4	76
valid_sources[0x02]	390154	1		T1	88		T3	319		T4	103
valid_sources[0x03]	388804	1		T1	56		T3	370		T4	83
valid_sources[0x04]	396912	1		T1	94		T3	275		T4	82
valid_sources[0x05]	391926	1		T1	79		T3	398		T4	86
valid_sources[0x06]	392879	1		T1	78		T3	382		T4	71
valid_sources[0x07]	391836	1		T1	74		T3	347		T4	73
valid_sources[0x08]	392233	1		T1	76		T3	494		T4	74
valid_sources[0x09]	804940	1		T1	82		T3	275		T4	82
valid_sources[0x0a]	389470	1		T1	78		T3	319		T4	70
valid_sources[0x0b]	394320	1		T1	68		T3	386		T4	90
valid_sources[0x0c]	393100	1		T1	93		T3	316		T4	119
valid_sources[0x0d]	392403	1		T1	94		T3	353		T4	78
valid_sources[0x0e]	394573	1		T1	105		T3	313		T4	81
valid_sources[0x0f]	387059	1		T1	93		T3	407		T4	110
valid_sources[0x10]	393571	1		T1	81		T3	312		T4	65
valid_sources[0x11]	512750	1		T1	68		T3	270		T4	81
valid_sources[0x12]	409670	1		T1	97		T3	448		T4	74
valid_sources[0x13]	391682	1		T1	92		T3	275		T4	78
valid_sources[0x14]	389336	1		T1	114		T3	332		T4	74
valid_sources[0x15]	414651	1		T1	92		T2	8322		T3	359
valid_sources[0x16]	391459	1		T1	123		T3	260		T4	104
valid_sources[0x17]	392579	1		T1	78		T3	341		T4	87
valid_sources[0x18]	395056	1		T1	91		T3	396		T4	126
valid_sources[0x19]	392668	1		T1	104		T3	341		T4	80
valid_sources[0x1a]	388007	1		T1	115		T3	295		T4	89
valid_sources[0x1b]	711824	1		T1	95		T3	343		T4	89
valid_sources[0x1c]	393319	1		T1	72		T3	436		T4	85
valid_sources[0x1d]	398897	1		T1	78		T3	299		T4	96
valid_sources[0x1e]	390533	1		T1	86		T3	231		T4	96
valid_sources[0x1f]	392997	1		T1	110		T3	426		T4	88
valid_sources[0x20]	390826	1		T1	105		T3	441		T4	75
valid_sources[0x21]	405409	1		T1	90		T3	327		T4	81
valid_sources[0x22]	393855	1		T1	92		T3	435		T4	75
valid_sources[0x23]	393630	1		T1	80		T3	339		T4	95
valid_sources[0x24]	510409	1		T1	98		T3	306		T4	72
valid_sources[0x25]	721283	1		T1	101		T3	419		T4	76
valid_sources[0x26]	388794	1		T1	102		T3	192		T4	98
valid_sources[0x27]	389552	1		T1	82		T3	372		T4	90
valid_sources[0x28]	391639	1		T1	102		T3	404		T4	93
valid_sources[0x29]	393479	1		T1	72		T3	364		T4	94
valid_sources[0x2a]	392562	1		T1	78		T3	423		T4	87
valid_sources[0x2b]	506608	1		T1	94		T3	441		T4	106
valid_sources[0x2c]	1565840	1		T1	70		T3	288		T4	75
valid_sources[0x2d]	392793	1		T1	113		T3	342		T4	97
valid_sources[0x2e]	393766	1		T1	89		T3	483		T4	75
valid_sources[0x2f]	395893	1		T1	96		T3	195		T4	102
valid_sources[0x30]	827642	1		T1	107		T3	339		T4	89
valid_sources[0x31]	389465	1		T1	98		T3	388		T4	78
valid_sources[0x32]	393244	1		T1	66		T3	484		T4	79
valid_sources[0x33]	393039	1		T1	94		T3	499		T4	78
valid_sources[0x34]	525330	1		T1	97		T3	526		T4	90
valid_sources[0x35]	412861	1		T1	64		T3	375		T4	86
valid_sources[0x36]	397732	1		T1	83		T3	347		T4	100
valid_sources[0x37]	386141	1		T1	91		T3	442		T4	99
valid_sources[0x38]	395148	1		T1	91		T3	364		T4	67
valid_sources[0x39]	392888	1		T1	95		T3	475		T4	100
valid_sources[0x3a]	391433	1		T1	98		T3	441		T4	84
valid_sources[0x3b]	390789	1		T1	84		T3	595		T4	83
valid_sources[0x3c]	393727	1		T1	76		T3	248		T4	85
valid_sources[0x3d]	410349	1		T1	78		T3	438		T4	72
valid_sources[0x3e]	1922555	1		T1	90		T3	325		T4	90
valid_sources[0x3f]	391004	1		T1	76		T3	233		T4	69
valid_sources[0x40]	389820	1		T1	86		T3	424		T4	75
valid_sources[0x41]	389416	1		T1	91		T3	410		T4	103
valid_sources[0x42]	395890	1		T1	69		T3	403		T4	84
valid_sources[0x43]	397657	1		T1	80		T3	229		T4	92
valid_sources[0x44]	393981	1		T1	86		T3	436		T4	65
valid_sources[0x45]	747336	1		T1	105		T3	359		T4	70
valid_sources[0x46]	393696	1		T1	85		T3	400		T4	85
valid_sources[0x47]	392992	1		T1	82		T3	373		T4	97
valid_sources[0x48]	390317	1		T1	107		T3	434		T4	86
valid_sources[0x49]	392275	1		T1	87		T3	336		T4	66
valid_sources[0x4a]	388781	1		T1	77		T3	261		T4	85
valid_sources[0x4b]	400954	1		T1	95		T3	291		T4	96
valid_sources[0x4c]	392082	1		T1	113		T3	306		T4	86
valid_sources[0x4d]	393055	1		T1	99		T3	348		T4	97
valid_sources[0x4e]	391516	1		T1	87		T3	317		T4	72
valid_sources[0x4f]	566412	1		T1	89		T3	257		T4	79
valid_sources[0x50]	394788	1		T1	94		T3	368		T4	68
valid_sources[0x51]	435618	1		T1	70		T3	421		T4	90
valid_sources[0x52]	472237	1		T1	95		T3	410		T4	86
valid_sources[0x53]	393151	1		T1	76		T3	343		T4	94
valid_sources[0x54]	440734	1		T1	115		T3	336		T4	108
valid_sources[0x55]	385216	1		T1	89		T3	484		T4	58
valid_sources[0x56]	391140	1		T1	108		T3	498		T4	81
valid_sources[0x57]	393070	1		T1	89		T3	257		T4	89
valid_sources[0x58]	501339	1		T1	106		T3	399		T4	88
valid_sources[0x59]	447443	1		T1	106		T3	414		T4	68
valid_sources[0x5a]	392641	1		T1	74		T3	447		T4	79
valid_sources[0x5b]	424524	1		T1	100		T3	278		T4	66
valid_sources[0x5c]	390832	1		T1	69		T3	347		T4	94
valid_sources[0x5d]	390843	1		T1	93		T3	390		T4	71
valid_sources[0x5e]	393045	1		T1	115		T3	335		T4	91
valid_sources[0x5f]	399791	1		T1	86		T3	268		T4	77
valid_sources[0x60]	1068433	1		T1	82		T3	425		T4	68
valid_sources[0x61]	390763	1		T1	83		T3	367		T4	94
valid_sources[0x62]	782196	1		T1	80		T3	271		T4	92
valid_sources[0x63]	387266	1		T1	102		T3	428		T4	78
valid_sources[0x64]	389337	1		T1	100		T3	403		T4	88
valid_sources[0x65]	389466	1		T1	81		T3	433		T4	91
valid_sources[0x66]	399730	1		T1	105		T3	583		T4	90
valid_sources[0x67]	429913	1		T1	86		T3	462		T4	61
valid_sources[0x68]	391589	1		T1	82		T3	398		T4	75
valid_sources[0x69]	392036	1		T1	90		T3	385		T4	72
valid_sources[0x6a]	396290	1		T1	66		T3	410		T4	66
valid_sources[0x6b]	394217	1		T1	97		T3	407		T4	79
valid_sources[0x6c]	391191	1		T1	85		T3	415		T4	83
valid_sources[0x6d]	655870	1		T1	125		T3	514		T4	92
valid_sources[0x6e]	405669	1		T1	93		T3	349		T4	82
valid_sources[0x6f]	389156	1		T1	90		T3	475		T4	91
valid_sources[0x70]	669992	1		T1	64		T3	315		T4	100
valid_sources[0x71]	391400	1		T1	100		T3	296		T4	67
valid_sources[0x72]	395369	1		T1	91		T3	362		T4	71
valid_sources[0x73]	397899	1		T1	104		T3	426		T4	102
valid_sources[0x74]	391144	1		T1	87		T3	398		T4	108
valid_sources[0x75]	399891	1		T1	105		T3	291		T4	89
valid_sources[0x76]	393608	1		T1	88		T3	272		T4	103
valid_sources[0x77]	391791	1		T1	96		T3	307		T4	70
valid_sources[0x78]	392170	1		T1	75		T3	487		T4	60
valid_sources[0x79]	389841	1		T1	94		T3	391		T4	96
valid_sources[0x7a]	2160959	1		T1	88		T3	276		T4	93
valid_sources[0x7b]	454122	1		T1	76		T3	345		T4	97
valid_sources[0x7c]	390439	1		T1	77		T3	246		T4	66
valid_sources[0x7d]	391693	1		T1	86		T3	350		T4	103
valid_sources[0x7e]	395722	1		T1	90		T3	371		T4	67
valid_sources[0x7f]	392480	1		T1	89		T3	573		T4	85
valid_sources[0x80]	395489	1		T1	73		T3	357		T4	88

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62240212

1

T1

11307

T2

4156

T3

47797

values[0x0]

all_enables

biggest_size

412022

1

T1

38

T2

16

T3

7

values[0x1]

all_enables

biggest_size

410896

1

T1

51

T2

20

T3

2