SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_timer_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 127278463 | 0 | T1 | 22749 | T2 | 8322 | T3 | 95476 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 127278222 | 1 | T1 | 22749 | T2 | 8322 | T3 | 95476 | |||
values[1] | 23 | 1 | T30 | 2 | T31 | 1 | T104 | 2 | |||
values[2] | 7 | 1 | T104 | 1 | T105 | 1 | T106 | 1 | |||
values[3] | 122 | 1 | T30 | 3 | T31 | 16 | T32 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 127278233 | 1 | T1 | 22749 | T2 | 8322 | T3 | 95476 | |||
values[1] | 38 | 1 | T30 | 1 | T31 | 3 | T32 | 2 | |||
values[2] | 8 | 1 | T31 | 1 | T32 | 1 | T107 | 2 | |||
values[3] | 108 | 1 | T30 | 4 | T31 | 8 | T32 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 127278113 | 1 | T1 | 22749 | T2 | 8322 | T3 | 95476 | |||
auto[TlIntgErrCmd] | 120 | 1 | T30 | 4 | T31 | 6 | T32 | 4 | |||
auto[TlIntgErrData] | 109 | 1 | T30 | 2 | T31 | 9 | T32 | 3 | |||
auto[TlIntgErrBoth] | 121 | 1 | T30 | 4 | T31 | 15 | T32 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |