Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1430829	0	0
cfg0_rd_A	2147483647	3130	0	0
compare_lower0_0_rd_A	2147483647	3283	0	0
compare_upper0_0_rd_A	2147483647	3094	0	0
ctrl_rd_A	2147483647	2822	0	0
intr_enable0_rd_A	2147483647	4178	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1430829	0	0
T13	627662	187191	0	0
T14	0	90618	0	0
T15	0	52270	0	0
T34	0	56215	0	0
T35	0	58404	0	0
T36	0	34919	0	0
T37	0	181945	0	0
T38	0	37687	0	0
T39	0	131517	0	0
T40	0	274515	0	0
T41	454346	0	0	0
T42	902535	0	0	0
T43	467176	0	0	0
T44	626517	0	0	0
T45	159361	0	0	0
T46	177273	0	0	0
T47	125940	0	0	0
T48	477716	0	0	0
T49	28558	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3130	0	0
T30	0	67	0	0
T33	0	3	0	0
T34	218846	570	0	0
T35	0	594	0	0
T38	0	346	0	0
T50	0	805	0	0
T51	0	15	0	0
T52	0	24	0	0
T53	0	5	0	0
T54	0	69	0	0
T55	142767	0	0	0
T56	156633	0	0	0
T57	286337	0	0	0
T58	162897	0	0	0
T59	251499	0	0	0
T60	441468	0	0	0
T61	272517	0	0	0
T62	115706	0	0	0
T63	641698	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3283	0	0
T30	0	34	0	0
T33	0	8	0	0
T34	218846	668	0	0
T35	0	665	0	0
T38	0	486	0	0
T50	0	809	0	0
T51	0	7	0	0
T52	0	20	0	0
T53	0	8	0	0
T54	0	41	0	0
T55	142767	0	0	0
T56	156633	0	0	0
T57	286337	0	0	0
T58	162897	0	0	0
T59	251499	0	0	0
T60	441468	0	0	0
T61	272517	0	0	0
T62	115706	0	0	0
T63	641698	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3094	0	0
T30	0	36	0	0
T33	0	9	0	0
T34	218846	499	0	0
T35	0	587	0	0
T38	0	463	0	0
T50	0	879	0	0
T51	0	11	0	0
T52	0	19	0	0
T54	0	41	0	0
T55	142767	0	0	0
T56	156633	0	0	0
T57	286337	0	0	0
T58	162897	0	0	0
T59	251499	0	0	0
T60	441468	0	0	0
T61	272517	0	0	0
T62	115706	0	0	0
T63	641698	0	0	0
T64	0	54	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2822	0	0
T30	0	38	0	0
T33	0	5	0	0
T34	218846	551	0	0
T35	0	533	0	0
T38	0	311	0	0
T50	0	743	0	0
T51	0	7	0	0
T52	0	33	0	0
T54	0	44	0	0
T55	142767	0	0	0
T56	156633	0	0	0
T57	286337	0	0	0
T58	162897	0	0	0
T59	251499	0	0	0
T60	441468	0	0	0
T61	272517	0	0	0
T62	115706	0	0	0
T63	641698	0	0	0
T64	0	66	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4178	0	0
T13	627662	0	0	0
T34	0	716	0	0
T35	0	681	0	0
T38	0	497	0	0
T41	454346	0	0	0
T42	902535	0	0	0
T43	467176	0	0	0
T44	626517	0	0	0
T45	159361	0	0	0
T46	177273	0	0	0
T47	125940	0	0	0
T48	477716	0	0	0
T65	617836	53	0	0
T66	0	69	0	0
T67	0	11	0	0
T68	0	65	0	0
T69	0	46	0	0
T70	0	32	0	0
T71	0	107	0	0