Unified Coverage Report :: Group :: dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg

Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv

19 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
rv_timer-0-prescale-0	100.00	1	100	1	64	64
rv_timer-0-prescale-1	100.00	1	100	1	64	64
rv_timer-0-prescale-10	100.00	1	100	1	64	64
rv_timer-0-prescale-11	100.00	1	100	1	64	64
rv_timer-0-prescale-2	100.00	1	100	1	64	64
rv_timer-0-prescale-3	100.00	1	100	1	64	64
rv_timer-0-prescale-4	100.00	1	100	1	64	64
rv_timer-0-prescale-5	100.00	1	100	1	64	64
rv_timer-0-prescale-6	100.00	1	100	1	64	64
rv_timer-0-prescale-7	100.00	1	100	1	64	64
rv_timer-0-prescale-8	100.00	1	100	1	64	64
rv_timer-0-prescale-9	100.00	1	100	1	64	64
rv_timer_sticky_intr_pin0	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max	100.00	1	100	1	64	64

---

Group Instance : rv_timer-0-prescale-0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-10

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-10

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-10

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-11

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-11

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-11

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-5

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-5

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-6

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-6

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-6

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-7

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-7

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-7

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-8

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-8

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-8

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-9

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-9

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-9

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer_sticky_intr_pin0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer_sticky_intr_pin0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer_sticky_intr_pin0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	228	1		T1	1		T3	1		T5	2
rising	226	1		T1	2		T5	2		T10	2

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	587	1		T1	2		T3	1		T4	2
auto[1]	624	1		T1	3		T2	1		T3	1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	199	1		T1	2		T5	2		T6	1
rising	216	1		T1	1		T5	2		T10	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	602	1		T1	2		T3	2		T4	2
auto[1]	609	1		T1	3		T2	1		T5	3

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	207	1		T1	1		T5	2		T10	1
rising	205	1		T1	1		T5	1		T6	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	607	1		T1	4		T2	1		T3	2
auto[1]	604	1		T1	1		T5	4		T6	3

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	221	1		T1	1		T3	1		T4	1
rising	222	1		T5	1		T6	2		T10	2

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	602	1		T1	3		T3	1		T4	1
auto[1]	609	1		T1	2		T2	1		T3	1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	217	1		T1	2		T3	1		T4	1
rising	215	1		T1	1		T5	1		T6	2

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	606	1		T1	3		T2	1		T3	1
auto[1]	605	1		T1	2		T3	1		T4	1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	227	1		T1	1		T3	1		T5	1
rising	225	1		T1	1		T5	2		T6	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	638	1		T1	3		T2	1		T3	1
auto[1]	573	1		T1	2		T3	1		T5	2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	221	1		T1	1		T10	1		T104	1
rising	202	1		T5	1		T6	1		T109	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	599	1		T1	3		T2	1		T3	2
auto[1]	612	1		T1	2		T5	3		T6	4

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	226	1		T1	2		T5	2		T6	1
rising	240	1		T1	1		T5	1		T6	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	613	1		T1	2		T3	2		T5	4
auto[1]	598	1		T1	3		T2	1		T4	2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	239	1		T1	1		T4	1		T5	1
rising	230	1		T1	2		T5	1		T6	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	607	1		T1	2		T3	2		T4	1
auto[1]	604	1		T1	3		T2	1		T4	1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	213	1		T5	1		T6	2		T10	2
rising	220	1		T1	1		T6	2		T10	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	551	1		T1	1		T2	1		T3	2
auto[1]	660	1		T1	4		T4	2		T5	1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	234	1		T1	1		T5	2		T6	1
rising	219	1		T1	1		T4	1		T5	2

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	624	1		T1	2		T3	2		T4	1
auto[1]	587	1		T1	3		T2	1		T4	1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	222	1		T1	1		T5	2		T6	1
rising	206	1		T1	1		T5	2		T6	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	601	1		T1	1		T5	3		T6	4
auto[1]	610	1		T1	4		T2	1		T3	2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	61	1		T2	1		T104	3		T123	2
rising	61	1		T2	1		T104	3		T123	2

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	7035	1		T1	17		T2	10		T3	17
auto[1]	87	1		T2	2		T104	4		T123	3

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	533007	1		T12	29247		T13	22843		T14	21178
rising	533005	1		T12	29247		T13	22844		T14	21178

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3633454	1		T12	202425		T13	159599		T14	146599
auto[1]	638053	1		T12	34865		T13	27364		T14	25334

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	1022404	1		T12	56916		T13	44899		T14	41192
rising	1022409	1		T12	56916		T13	44899		T14	41193

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2541800	1		T12	140784		T13	111124		T14	102371
auto[1]	1729707	1		T12	96506		T13	75839		T14	69562

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	1022404	1		T12	56916		T13	44899		T14	41192
rising	1022409	1		T12	56916		T13	44899		T14	41193

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2541800	1		T12	140784		T13	111124		T14	102371
auto[1]	1729707	1		T12	96506		T13	75839		T14	69562

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	1041613	1		T12	57625		T13	45824		T14	41783
rising	1041621	1		T12	57626		T13	45824		T14	41784

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2298575	1		T12	127077		T13	99959		T14	91572
auto[1]	1972932	1		T12	110213		T13	87004		T14	80361

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	754600	1		T12	42199		T13	33331		T14	30517
rising	754594	1		T12	42199		T13	33331		T14	30516

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3281969	1		T12	181667		T13	143314		T14	132101
auto[1]	989538	1		T12	55623		T13	43649		T14	39832

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	770464	1		T12	42654		T13	33855		T14	31091
rising	770465	1		T12	42654		T13	33855		T14	31092

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3262475	1		T12	181462		T13	142763		T14	131280
auto[1]	1009032	1		T12	55828		T13	44200		T14	40653