Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2832452	0	0
cfg0_rd_A	2147483647	4688	0	0
compare_lower0_0_rd_A	2147483647	4682	0	0
compare_upper0_0_rd_A	2147483647	4646	0	0
ctrl_rd_A	2147483647	4351	0	0
intr_enable0_rd_A	2147483647	5931	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2832452	0	0
T12	581729	159238	0	0
T13	0	124243	0	0
T14	0	114554	0	0
T36	0	174398	0	0
T37	0	124197	0	0
T38	0	57738	0	0
T39	0	455411	0	0
T40	0	161391	0	0
T41	0	233820	0	0
T42	0	267852	0	0
T43	493673	0	0	0
T44	342807	0	0	0
T45	725303	0	0	0
T46	116765	0	0	0
T47	815021	0	0	0
T48	670566	0	0	0
T49	203844	0	0	0
T50	423071	0	0	0
T51	103838	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4688	0	0
T12	581729	830	0	0
T14	0	616	0	0
T30	0	41	0	0
T32	0	33	0	0
T33	0	227	0	0
T34	0	4	0	0
T40	0	1856	0	0
T43	493673	0	0	0
T44	342807	0	0	0
T45	725303	0	0	0
T46	116765	0	0	0
T47	815021	0	0	0
T48	670566	0	0	0
T49	203844	0	0	0
T50	423071	0	0	0
T51	103838	0	0	0
T52	0	29	0	0
T53	0	31	0	0
T54	0	27	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4682	0	0
T12	581729	1092	0	0
T14	0	625	0	0
T30	0	42	0	0
T32	0	51	0	0
T33	0	219	0	0
T34	0	9	0	0
T40	0	1703	0	0
T43	493673	0	0	0
T44	342807	0	0	0
T45	725303	0	0	0
T46	116765	0	0	0
T47	815021	0	0	0
T48	670566	0	0	0
T49	203844	0	0	0
T50	423071	0	0	0
T51	103838	0	0	0
T52	0	30	0	0
T53	0	33	0	0
T54	0	30	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4646	0	0
T12	581729	879	0	0
T14	0	681	0	0
T30	0	49	0	0
T32	0	99	0	0
T33	0	235	0	0
T40	0	1717	0	0
T43	493673	0	0	0
T44	342807	0	0	0
T45	725303	0	0	0
T46	116765	0	0	0
T47	815021	0	0	0
T48	670566	0	0	0
T49	203844	0	0	0
T50	423071	0	0	0
T51	103838	0	0	0
T52	0	17	0	0
T53	0	15	0	0
T54	0	24	0	0
T55	0	13	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4351	0	0
T12	581729	884	0	0
T14	0	540	0	0
T30	0	48	0	0
T32	0	42	0	0
T33	0	223	0	0
T34	0	4	0	0
T40	0	1710	0	0
T43	493673	0	0	0
T44	342807	0	0	0
T45	725303	0	0	0
T46	116765	0	0	0
T47	815021	0	0	0
T48	670566	0	0	0
T49	203844	0	0	0
T50	423071	0	0	0
T51	103838	0	0	0
T52	0	21	0	0
T53	0	25	0	0
T54	0	17	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5931	0	0
T12	581729	923	0	0
T14	0	673	0	0
T26	0	119	0	0
T40	0	2204	0	0
T43	493673	97	0	0
T44	342807	0	0	0
T45	725303	0	0	0
T46	116765	0	0	0
T47	815021	0	0	0
T48	670566	28	0	0
T49	203844	0	0	0
T50	423071	0	0	0
T51	103838	0	0	0
T56	0	50	0	0
T57	0	35	0	0
T58	0	44	0	0
T59	0	27	0	0