Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66939708	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	67598709	1		T1	405795		T2	358195		T3	14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	133967192	1		T1	810407		T2	715466		T3	20
values[0x0]	272765	1		T1	19		T2	24		T3	9
values[0x1]	298460	1		T1	13		T2	16		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53477798	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	81060619	1		T1	487072		T2	429465		T3	14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	396174	1		T1	3171		T2	2696		T5	4
valid_sources[0x01]	403102	1		T1	3173		T2	2666		T8	20
valid_sources[0x02]	393755	1		T1	3144		T2	3061		T8	6
valid_sources[0x03]	395698	1		T1	3173		T2	2830		T8	5
valid_sources[0x04]	393232	1		T1	3093		T2	2253		T3	1
valid_sources[0x05]	394341	1		T1	3170		T2	2780		T8	1
valid_sources[0x06]	396446	1		T1	3138		T2	2553		T8	9
valid_sources[0x07]	395954	1		T1	3158		T2	2903		T8	7
valid_sources[0x08]	395537	1		T1	3146		T2	3034		T8	5
valid_sources[0x09]	396678	1		T1	3057		T2	2577		T8	14
valid_sources[0x0a]	396251	1		T1	3140		T2	2339		T3	1
valid_sources[0x0b]	395273	1		T1	3194		T2	3287		T3	1
valid_sources[0x0c]	1405065	1		T1	3215		T2	3118		T8	12
valid_sources[0x0d]	395230	1		T1	3123		T2	3143		T8	11
valid_sources[0x0e]	397471	1		T1	3180		T2	3014		T8	9
valid_sources[0x0f]	393605	1		T1	3237		T2	3098		T5	1
valid_sources[0x10]	396915	1		T1	3092		T2	2756		T5	1
valid_sources[0x11]	394732	1		T1	3220		T2	2616		T8	2
valid_sources[0x12]	961134	1		T1	3166		T2	3033		T8	22
valid_sources[0x13]	407196	1		T1	3181		T2	2484		T8	2
valid_sources[0x14]	390796	1		T1	3166		T2	2626		T8	11
valid_sources[0x15]	397664	1		T1	3105		T2	2601		T8	3
valid_sources[0x16]	392582	1		T1	3146		T2	3011		T8	11
valid_sources[0x17]	396548	1		T1	3220		T2	2760		T8	8
valid_sources[0x18]	394150	1		T1	3220		T2	2313		T8	6
valid_sources[0x19]	396368	1		T1	3255		T2	2827		T8	2
valid_sources[0x1a]	395789	1		T1	3176		T2	2714		T8	20
valid_sources[0x1b]	735143	1		T1	3174		T2	2887		T8	7
valid_sources[0x1c]	398542	1		T1	3153		T2	2755		T8	13
valid_sources[0x1d]	575754	1		T1	3243		T2	2897		T8	19
valid_sources[0x1e]	396530	1		T1	3139		T2	2891		T5	2
valid_sources[0x1f]	395634	1		T1	3184		T2	2823		T8	9
valid_sources[0x20]	396912	1		T1	3221		T2	2672		T8	5
valid_sources[0x21]	399976	1		T1	3036		T2	2593		T8	14
valid_sources[0x22]	410662	1		T1	3139		T2	2738		T8	4
valid_sources[0x23]	396311	1		T1	3185		T2	2914		T8	10
valid_sources[0x24]	395020	1		T1	3216		T2	2902		T8	7
valid_sources[0x25]	632407	1		T1	3214		T2	2955		T3	2
valid_sources[0x26]	392350	1		T1	3224		T2	2882		T8	10
valid_sources[0x27]	424668	1		T1	3213		T2	2935		T3	1
valid_sources[0x28]	394630	1		T1	3190		T2	2492		T8	5
valid_sources[0x29]	395333	1		T1	3121		T2	2804		T8	15
valid_sources[0x2a]	446673	1		T1	3202		T2	2264		T3	2
valid_sources[0x2b]	405531	1		T1	3065		T2	2571		T8	7
valid_sources[0x2c]	394596	1		T1	3121		T2	2906		T8	5
valid_sources[0x2d]	397977	1		T1	3186		T2	3073		T8	12
valid_sources[0x2e]	394109	1		T1	3196		T2	2764		T8	10
valid_sources[0x2f]	394782	1		T1	3167		T2	2385		T5	1
valid_sources[0x30]	396202	1		T1	3143		T2	2652		T8	6
valid_sources[0x31]	399069	1		T1	3154		T2	3003		T8	1
valid_sources[0x32]	393840	1		T1	3160		T2	2749		T8	12
valid_sources[0x33]	2200075	1		T1	3163		T2	2534		T8	8
valid_sources[0x34]	663056	1		T1	3196		T2	2914		T4	267512
valid_sources[0x35]	398149	1		T1	3244		T2	2971		T8	9
valid_sources[0x36]	402657	1		T1	3277		T2	2699		T3	1
valid_sources[0x37]	901843	1		T1	3146		T2	2594		T8	3
valid_sources[0x38]	397951	1		T1	3111		T2	2779		T8	8
valid_sources[0x39]	393632	1		T1	3177		T2	3140		T8	5
valid_sources[0x3a]	399076	1		T1	3195		T2	2717		T5	1
valid_sources[0x3b]	396001	1		T1	3209		T2	3139		T8	3
valid_sources[0x3c]	392913	1		T1	3215		T2	3034		T8	15
valid_sources[0x3d]	396110	1		T1	3123		T2	2616		T8	4
valid_sources[0x3e]	395505	1		T1	3214		T2	2529		T8	8
valid_sources[0x3f]	401406	1		T1	3101		T2	2772		T5	1
valid_sources[0x40]	990949	1		T1	3170		T2	2756		T8	25
valid_sources[0x41]	428469	1		T1	3141		T2	2797		T7	32278
valid_sources[0x42]	397125	1		T1	3149		T2	3058		T8	15
valid_sources[0x43]	396628	1		T1	3082		T2	2503		T8	6
valid_sources[0x44]	537032	1		T1	3197		T2	3033		T8	12
valid_sources[0x45]	392486	1		T1	3253		T2	2662		T8	10
valid_sources[0x46]	396495	1		T1	3178		T2	3088		T8	11
valid_sources[0x47]	393798	1		T1	3095		T2	2623		T8	5
valid_sources[0x48]	924650	1		T1	3150		T2	2891		T8	5
valid_sources[0x49]	394306	1		T1	3177		T2	2560		T8	24
valid_sources[0x4a]	968856	1		T1	3070		T2	2787		T8	5
valid_sources[0x4b]	393042	1		T1	3149		T2	2612		T8	5
valid_sources[0x4c]	400528	1		T1	3177		T2	2718		T9	29
valid_sources[0x4d]	1316291	1		T1	3115		T2	2734		T8	10
valid_sources[0x4e]	394893	1		T1	3065		T2	3049		T8	6
valid_sources[0x4f]	401767	1		T1	3227		T2	3096		T8	2
valid_sources[0x50]	395662	1		T1	3123		T2	2772		T3	1
valid_sources[0x51]	397781	1		T1	3161		T2	2819		T8	2
valid_sources[0x52]	398857	1		T1	3109		T2	2628		T8	3
valid_sources[0x53]	396564	1		T1	3164		T2	2625		T8	9
valid_sources[0x54]	398653	1		T1	3042		T2	2919		T3	1
valid_sources[0x55]	396367	1		T1	3180		T2	2302		T8	4
valid_sources[0x56]	397514	1		T1	3134		T2	2339		T8	6
valid_sources[0x57]	401869	1		T1	3188		T2	2970		T8	9
valid_sources[0x58]	426439	1		T1	3213		T2	2939		T8	13
valid_sources[0x59]	395635	1		T1	3170		T2	3047		T8	20
valid_sources[0x5a]	398776	1		T1	3250		T2	2490		T8	32
valid_sources[0x5b]	395608	1		T1	3077		T2	2846		T8	17
valid_sources[0x5c]	398182	1		T1	3294		T2	2939		T8	3
valid_sources[0x5d]	452107	1		T1	3234		T2	2738		T8	13
valid_sources[0x5e]	397198	1		T1	3229		T2	2485		T9	35
valid_sources[0x5f]	418099	1		T1	3228		T2	2828		T9	23
valid_sources[0x60]	423737	1		T1	3175		T2	2783		T8	15
valid_sources[0x61]	397924	1		T1	3154		T2	2636		T5	2
valid_sources[0x62]	850224	1		T1	3130		T2	2461		T8	12
valid_sources[0x63]	396138	1		T1	3186		T2	3261		T8	5
valid_sources[0x64]	399193	1		T1	3143		T2	3032		T8	12
valid_sources[0x65]	452072	1		T1	3185		T2	2645		T5	1
valid_sources[0x66]	394157	1		T1	3184		T2	2842		T8	7
valid_sources[0x67]	391402	1		T1	3149		T2	2885		T3	1
valid_sources[0x68]	1847212	1		T1	3128		T2	2823		T8	9
valid_sources[0x69]	396484	1		T1	3184		T2	2998		T3	1
valid_sources[0x6a]	396506	1		T1	3120		T2	3244		T3	1
valid_sources[0x6b]	395309	1		T1	3108		T2	2985		T8	5
valid_sources[0x6c]	866786	1		T1	3162		T2	2627		T3	1
valid_sources[0x6d]	392367	1		T1	3084		T2	2596		T8	1
valid_sources[0x6e]	395385	1		T1	3198		T2	2942		T8	11
valid_sources[0x6f]	397586	1		T1	3179		T2	2797		T8	16
valid_sources[0x70]	395432	1		T1	3070		T2	2580		T5	1
valid_sources[0x71]	1029293	1		T1	3266		T2	2948		T8	7
valid_sources[0x72]	397610	1		T1	3261		T2	3095		T8	16
valid_sources[0x73]	1121744	1		T1	3195		T2	2698		T9	19
valid_sources[0x74]	400000	1		T1	3106		T2	2789		T8	4
valid_sources[0x75]	398279	1		T1	3118		T2	2675		T8	9
valid_sources[0x76]	398242	1		T1	3305		T2	2569		T8	24
valid_sources[0x77]	397803	1		T1	3084		T2	2771		T8	7
valid_sources[0x78]	394480	1		T1	3231		T2	2739		T9	32
valid_sources[0x79]	397026	1		T1	3135		T2	2518		T8	13
valid_sources[0x7a]	416849	1		T1	3023		T2	2585		T8	6
valid_sources[0x7b]	455774	1		T1	3041		T2	2556		T8	3
valid_sources[0x7c]	1175244	1		T1	3113		T2	2843		T8	21
valid_sources[0x7d]	866907	1		T1	3117		T2	2673		T5	1
valid_sources[0x7e]	409015	1		T1	3168		T2	2807		T8	11
valid_sources[0x7f]	969366	1		T1	3196		T2	2520		T9	32
valid_sources[0x80]	395195	1		T1	3181		T2	2737		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

67071017

1

T1

405771

T2

358168

T3

10

values[0x0]

all_enables

biggest_size

265214

1

T1

17

T2

18

T3

4

values[0x1]

all_enables

biggest_size

262478

1

T1

7

T2

9

T4

15