Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	885643	0	0
cfg0_rd_A	2147483647	4082	0	0
compare_lower0_0_rd_A	2147483647	4268	0	0
compare_upper0_0_rd_A	2147483647	3954	0	0
ctrl_rd_A	2147483647	3706	0	0
intr_enable0_rd_A	2147483647	5089	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	885643	0	0
T11	160971	41850	0	0
T12	0	252556	0	0
T13	0	139025	0	0
T28	0	9	0	0
T35	0	250762	0	0
T36	0	102406	0	0
T37	0	85153	0	0
T38	0	1042	0	0
T39	0	58	0	0
T40	0	1024	0	0
T41	648051	0	0	0
T42	621122	0	0	0
T43	114547	0	0	0
T44	151951	0	0	0
T45	5997	0	0	0
T46	493732	0	0	0
T47	122381	0	0	0
T48	669618	0	0	0
T49	167731	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4082	0	0
T31	0	10	0	0
T35	990622	2338	0	0
T36	241984	0	0	0
T50	0	26	0	0
T51	0	8	0	0
T52	0	58	0	0
T53	0	8	0	0
T54	0	21	0	0
T55	0	1	0	0
T56	0	6	0	0
T57	0	169	0	0
T58	116933	0	0	0
T59	171465	0	0	0
T60	188295	0	0	0
T61	280395	0	0	0
T62	770094	0	0	0
T63	243877	0	0	0
T64	385949	0	0	0
T65	312196	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4268	0	0
T31	0	9	0	0
T35	990622	2840	0	0
T36	241984	0	0	0
T50	0	1	0	0
T51	0	5	0	0
T52	0	74	0	0
T54	0	10	0	0
T56	0	23	0	0
T57	0	114	0	0
T58	116933	0	0	0
T59	171465	0	0	0
T60	188295	0	0	0
T61	280395	0	0	0
T62	770094	0	0	0
T63	243877	0	0	0
T64	385949	0	0	0
T65	312196	0	0	0
T66	0	21	0	0
T67	0	47	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3954	0	0
T31	0	4	0	0
T35	990622	2397	0	0
T36	241984	0	0	0
T50	0	4	0	0
T51	0	5	0	0
T52	0	78	0	0
T54	0	48	0	0
T55	0	6	0	0
T56	0	14	0	0
T57	0	120	0	0
T58	116933	0	0	0
T59	171465	0	0	0
T60	188295	0	0	0
T61	280395	0	0	0
T62	770094	0	0	0
T63	243877	0	0	0
T64	385949	0	0	0
T65	312196	0	0	0
T66	0	21	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3706	0	0
T31	0	5	0	0
T35	990622	2318	0	0
T36	241984	0	0	0
T50	0	13	0	0
T51	0	4	0	0
T52	0	16	0	0
T53	0	8	0	0
T54	0	13	0	0
T56	0	4	0	0
T57	0	116	0	0
T58	116933	0	0	0
T59	171465	0	0	0
T60	188295	0	0	0
T61	280395	0	0	0
T62	770094	0	0	0
T63	243877	0	0	0
T64	385949	0	0	0
T65	312196	0	0	0
T66	0	16	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5089	0	0
T35	0	2970	0	0
T46	493732	20	0	0
T47	122381	0	0	0
T48	669618	0	0	0
T49	167731	0	0	0
T68	0	54	0	0
T69	0	18	0	0
T70	0	14	0	0
T71	0	45	0	0
T72	0	88	0	0
T73	0	40	0	0
T74	0	55	0	0
T75	0	30	0	0
T76	156838	0	0	0
T77	954014	0	0	0
T78	142610	0	0	0
T79	120022	0	0	0
T80	285096	0	0	0
T81	115248	0	0	0