Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1699210	0	0
cfg0_rd_A	2147483647	7525	0	0
compare_lower0_0_rd_A	2147483647	7770	0	0
compare_upper0_0_rd_A	2147483647	6970	0	0
ctrl_rd_A	2147483647	7389	0	0
intr_enable0_rd_A	2147483647	9465	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1699210	0	0
T12	622406	115350	0	0
T13	0	62338	0	0
T14	0	147693	0	0
T28	0	103835	0	0
T34	0	51032	0	0
T35	0	75297	0	0
T36	0	156101	0	0
T37	0	287552	0	0
T38	0	135921	0	0
T39	0	35725	0	0
T40	1590	0	0	0
T41	193782	0	0	0
T42	748364	0	0	0
T43	663128	0	0	0
T44	352639	0	0	0
T45	560589	0	0	0
T46	574767	0	0	0
T47	554993	0	0	0
T48	855170	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7525	0	0
T12	622406	1176	0	0
T13	0	670	0	0
T29	0	143	0	0
T31	0	126	0	0
T34	0	442	0	0
T36	0	1569	0	0
T38	0	1242	0	0
T40	1590	0	0	0
T41	193782	0	0	0
T42	748364	0	0	0
T43	663128	0	0	0
T44	352639	0	0	0
T45	560589	0	0	0
T46	574767	0	0	0
T47	554993	0	0	0
T48	855170	0	0	0
T49	0	5	0	0
T50	0	13	0	0
T51	0	57	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7770	0	0
T12	622406	1223	0	0
T13	0	814	0	0
T29	0	114	0	0
T31	0	73	0	0
T34	0	462	0	0
T36	0	1751	0	0
T38	0	1441	0	0
T40	1590	0	0	0
T41	193782	0	0	0
T42	748364	0	0	0
T43	663128	0	0	0
T44	352639	0	0	0
T45	560589	0	0	0
T46	574767	0	0	0
T47	554993	0	0	0
T48	855170	0	0	0
T50	0	15	0	0
T51	0	62	0	0
T52	0	47	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6970	0	0
T12	622406	967	0	0
T13	0	697	0	0
T29	0	111	0	0
T31	0	65	0	0
T34	0	511	0	0
T36	0	1606	0	0
T38	0	1169	0	0
T40	1590	0	0	0
T41	193782	0	0	0
T42	748364	0	0	0
T43	663128	0	0	0
T44	352639	0	0	0
T45	560589	0	0	0
T46	574767	0	0	0
T47	554993	0	0	0
T48	855170	0	0	0
T49	0	5	0	0
T50	0	17	0	0
T51	0	75	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7389	0	0
T12	622406	1220	0	0
T13	0	593	0	0
T29	0	112	0	0
T31	0	57	0	0
T34	0	546	0	0
T36	0	1626	0	0
T38	0	1293	0	0
T40	1590	0	0	0
T41	193782	0	0	0
T42	748364	0	0	0
T43	663128	0	0	0
T44	352639	0	0	0
T45	560589	0	0	0
T46	574767	0	0	0
T47	554993	0	0	0
T48	855170	0	0	0
T49	0	6	0	0
T50	0	17	0	0
T51	0	72	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9465	0	0
T12	622406	1375	0	0
T13	0	936	0	0
T33	783126	90	0	0
T34	0	623	0	0
T40	1590	0	0	0
T41	193782	0	0	0
T42	748364	0	0	0
T43	663128	0	0	0
T44	352639	0	0	0
T45	560589	0	0	0
T53	0	70	0	0
T54	0	38	0	0
T55	0	91	0	0
T56	0	37	0	0
T57	0	133	0	0
T58	0	13	0	0
T59	111755	0	0	0
T60	467454	0	0	0