Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	70352527	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	71658743	1		T1	155823		T2	673449		T3	255475

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	140874584	1		T1	311400		T2	134455		T3	509911
values[0x0]	541032	1		T1	22		T2	92		T3	75
values[0x1]	595654	1		T1	20		T2	86		T3	81

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56191403	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	85819867	1		T1	186980		T2	808263		T3	306938

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	466288	1		T2	4984		T4	2970		T5	9981
valid_sources[0x01]	466452	1		T2	5251		T4	2950		T5	9971
valid_sources[0x02]	468622	1		T2	5182		T4	2932		T5	9989
valid_sources[0x03]	513630	1		T2	5204		T4	3034		T5	9798
valid_sources[0x04]	476045	1		T2	5546		T4	3087		T5	10040
valid_sources[0x05]	473071	1		T2	5098		T4	3149		T5	10067
valid_sources[0x06]	469755	1		T2	5338		T4	3058		T5	9863
valid_sources[0x07]	470971	1		T2	5775		T4	3036		T5	9933
valid_sources[0x08]	466651	1		T2	5280		T4	3045		T5	10019
valid_sources[0x09]	468887	1		T2	5466		T4	3035		T5	9864
valid_sources[0x0a]	466247	1		T2	5424		T4	3036		T5	9977
valid_sources[0x0b]	483097	1		T2	4980		T4	2979		T5	9780
valid_sources[0x0c]	471842	1		T2	5148		T4	3044		T5	9780
valid_sources[0x0d]	471175	1		T2	5356		T4	3035		T5	10032
valid_sources[0x0e]	471339	1		T2	5367		T4	3014		T5	9766
valid_sources[0x0f]	476036	1		T2	5216		T4	2941		T5	10165
valid_sources[0x10]	488391	1		T2	5256		T4	3066		T5	9949
valid_sources[0x11]	639739	1		T2	5329		T4	3096		T5	9852
valid_sources[0x12]	485783	1		T2	5399		T4	2970		T5	9977
valid_sources[0x13]	466362	1		T2	5149		T4	3007		T5	10011
valid_sources[0x14]	1068495	1		T2	5209		T4	3012		T5	9995
valid_sources[0x15]	470988	1		T2	5134		T4	3021		T5	9783
valid_sources[0x16]	466495	1		T2	5475		T4	3013		T5	9674
valid_sources[0x17]	467844	1		T2	5118		T4	3114		T5	10015
valid_sources[0x18]	468744	1		T2	5110		T4	3109		T5	10015
valid_sources[0x19]	508665	1		T2	5249		T4	3043		T5	9843
valid_sources[0x1a]	466164	1		T2	5358		T4	3027		T5	10093
valid_sources[0x1b]	467230	1		T2	5139		T4	2965		T5	9813
valid_sources[0x1c]	467105	1		T2	5518		T4	3120		T5	9984
valid_sources[0x1d]	471187	1		T2	5385		T4	3067		T5	9831
valid_sources[0x1e]	466923	1		T2	5273		T4	2993		T5	9855
valid_sources[0x1f]	468469	1		T2	5070		T4	2928		T5	9883
valid_sources[0x20]	471591	1		T2	5312		T4	2971		T5	10111
valid_sources[0x21]	464654	1		T2	5075		T4	3112		T5	10066
valid_sources[0x22]	470686	1		T2	5149		T4	2939		T5	10060
valid_sources[0x23]	465809	1		T2	5325		T4	3013		T5	10107
valid_sources[0x24]	467368	1		T2	5257		T4	3079		T5	10207
valid_sources[0x25]	469709	1		T2	5431		T4	3111		T5	9788
valid_sources[0x26]	472180	1		T2	5206		T4	3097		T5	9972
valid_sources[0x27]	464902	1		T2	5336		T4	2980		T5	10010
valid_sources[0x28]	514242	1		T2	4864		T4	3008		T5	9990
valid_sources[0x29]	469429	1		T2	4911		T4	3120		T5	10008
valid_sources[0x2a]	472619	1		T2	5142		T4	2936		T5	10062
valid_sources[0x2b]	468177	1		T2	5258		T4	2992		T5	10018
valid_sources[0x2c]	537903	1		T2	5274		T4	3102		T5	9777
valid_sources[0x2d]	469495	1		T2	5170		T4	3089		T5	10128
valid_sources[0x2e]	468999	1		T2	5488		T4	3044		T5	10104
valid_sources[0x2f]	465606	1		T2	5156		T4	2974		T5	9904
valid_sources[0x30]	710202	1		T2	4992		T4	3008		T5	10041
valid_sources[0x31]	1029909	1		T2	5393		T4	2964		T5	10053
valid_sources[0x32]	465369	1		T2	5309		T4	3085		T5	10040
valid_sources[0x33]	555425	1		T2	4977		T4	3112		T5	9905
valid_sources[0x34]	658614	1		T2	5438		T4	2938		T5	9886
valid_sources[0x35]	469182	1		T2	5371		T4	3039		T5	9842
valid_sources[0x36]	477172	1		T2	4849		T4	3053		T5	9903
valid_sources[0x37]	466168	1		T2	5324		T4	2988		T5	10112
valid_sources[0x38]	468973	1		T2	5323		T4	2980		T5	9869
valid_sources[0x39]	468376	1		T2	5152		T4	3074		T5	9794
valid_sources[0x3a]	467722	1		T2	5332		T4	3102		T5	9870
valid_sources[0x3b]	467897	1		T2	5304		T4	2966		T5	9879
valid_sources[0x3c]	470900	1		T2	5228		T4	2951		T5	9899
valid_sources[0x3d]	901496	1		T2	5194		T4	3042		T5	10051
valid_sources[0x3e]	464384	1		T2	5176		T4	2966		T5	10105
valid_sources[0x3f]	465705	1		T2	5255		T4	2942		T5	9796
valid_sources[0x40]	490968	1		T2	5298		T4	2992		T5	9867
valid_sources[0x41]	465994	1		T2	5545		T4	3089		T5	9976
valid_sources[0x42]	466221	1		T2	5235		T4	3037		T5	9953
valid_sources[0x43]	467388	1		T2	5086		T4	3005		T5	9839
valid_sources[0x44]	470236	1		T2	5162		T4	3056		T5	9902
valid_sources[0x45]	890154	1		T2	5105		T4	2893		T5	9948
valid_sources[0x46]	468012	1		T2	5304		T4	3108		T5	10080
valid_sources[0x47]	467209	1		T2	5384		T4	3028		T5	9957
valid_sources[0x48]	531640	1		T2	5355		T4	2962		T5	10121
valid_sources[0x49]	467693	1		T2	5089		T4	2931		T5	9975
valid_sources[0x4a]	473430	1		T2	5250		T4	2996		T5	9908
valid_sources[0x4b]	465940	1		T2	5046		T4	3016		T5	9742
valid_sources[0x4c]	471398	1		T2	5194		T4	3057		T5	10190
valid_sources[0x4d]	466707	1		T2	5522		T4	2927		T5	10031
valid_sources[0x4e]	475147	1		T2	5167		T4	3013		T5	10015
valid_sources[0x4f]	487274	1		T2	5447		T4	2989		T5	9873
valid_sources[0x50]	468202	1		T2	5272		T4	3022		T5	9825
valid_sources[0x51]	466759	1		T2	4886		T4	3007		T5	9898
valid_sources[0x52]	472599	1		T2	5000		T4	2997		T5	9963
valid_sources[0x53]	470230	1		T2	5218		T4	3037		T5	9973
valid_sources[0x54]	467844	1		T2	5278		T4	3031		T5	10175
valid_sources[0x55]	471487	1		T2	5171		T4	3068		T5	9866
valid_sources[0x56]	467248	1		T2	5370		T4	3089		T5	9981
valid_sources[0x57]	471008	1		T2	5328		T4	2979		T5	9982
valid_sources[0x58]	467089	1		T2	5214		T4	3014		T5	9904
valid_sources[0x59]	2236027	1		T2	5477		T4	2981		T5	9873
valid_sources[0x5a]	469240	1		T2	5137		T4	3030		T5	10068
valid_sources[0x5b]	467999	1		T2	5112		T4	2955		T5	9813
valid_sources[0x5c]	467550	1		T2	5417		T4	2979		T5	10274
valid_sources[0x5d]	466800	1		T2	5064		T4	3097		T5	9887
valid_sources[0x5e]	466960	1		T2	5035		T4	2885		T5	9804
valid_sources[0x5f]	468146	1		T2	5159		T4	3001		T5	10029
valid_sources[0x60]	485902	1		T2	5348		T4	2954		T5	9880
valid_sources[0x61]	531715	1		T2	5026		T4	3070		T5	9815
valid_sources[0x62]	468671	1		T2	5375		T4	2942		T5	10033
valid_sources[0x63]	466099	1		T2	5514		T4	3056		T5	9738
valid_sources[0x64]	466861	1		T2	5059		T4	3113		T5	9725
valid_sources[0x65]	604363	1		T2	5290		T4	3089		T5	10033
valid_sources[0x66]	465866	1		T2	5327		T4	2966		T5	9795
valid_sources[0x67]	476909	1		T2	5260		T4	3070		T5	9801
valid_sources[0x68]	467701	1		T2	5405		T4	2966		T5	9955
valid_sources[0x69]	464558	1		T2	5026		T4	3053		T5	10175
valid_sources[0x6a]	2961391	1		T2	5220		T4	2984		T5	9835
valid_sources[0x6b]	778297	1		T1	311442		T2	5144		T4	3020
valid_sources[0x6c]	466239	1		T2	5353		T4	3046		T5	9995
valid_sources[0x6d]	462291	1		T2	5193		T4	3070		T5	10002
valid_sources[0x6e]	475628	1		T2	5209		T4	3071		T5	10047
valid_sources[0x6f]	632108	1		T2	5226		T4	3000		T5	9891
valid_sources[0x70]	472803	1		T2	5185		T4	3015		T5	10012
valid_sources[0x71]	479995	1		T2	5207		T4	3050		T5	9666
valid_sources[0x72]	466210	1		T2	5228		T4	2984		T5	9946
valid_sources[0x73]	476459	1		T2	5380		T4	2988		T5	9746
valid_sources[0x74]	468257	1		T2	5301		T4	2949		T5	10325
valid_sources[0x75]	469459	1		T2	5004		T4	3044		T5	10200
valid_sources[0x76]	468254	1		T2	5427		T4	2953		T5	9991
valid_sources[0x77]	465140	1		T2	5528		T4	3064		T5	9815
valid_sources[0x78]	696893	1		T2	5160		T4	3028		T5	9942
valid_sources[0x79]	642344	1		T2	5470		T4	2960		T5	10027
valid_sources[0x7a]	584918	1		T2	5203		T4	2982		T5	9932
valid_sources[0x7b]	463294	1		T2	5149		T4	3002		T5	9942
valid_sources[0x7c]	465507	1		T2	5433		T4	2989		T5	9831
valid_sources[0x7d]	467112	1		T2	5288		T4	3066		T5	9878
valid_sources[0x7e]	509027	1		T2	5387		T4	3101		T5	9979
valid_sources[0x7f]	529894	1		T2	5212		T4	3066		T5	9913
valid_sources[0x80]	467445	1		T2	5005		T4	2992		T5	9953

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70601186

1

T1

155793

T2

673312

T3

255375

values[0x0]

all_enables

biggest_size

530022

1

T1

17

T2

76

T3

49

values[0x1]

all_enables

biggest_size

527535

1

T1

13

T2

61

T3

51