Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1845979	0	0
cfg0_rd_A	2147483647	2566	0	0
compare_lower0_0_rd_A	2147483647	2330	0	0
compare_upper0_0_rd_A	2147483647	2321	0	0
ctrl_rd_A	2147483647	2245	0	0
intr_enable0_rd_A	2147483647	3084	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1845979	0	0
T11	867038	321734	0	0
T12	0	246214	0	0
T13	0	430308	0	0
T14	8414	0	0	0
T19	652521	0	0	0
T20	326974	0	0	0
T21	340362	0	0	0
T22	16553	0	0	0
T23	693914	0	0	0
T24	980096	0	0	0
T28	0	12	0	0
T34	0	92196	0	0
T35	0	61960	0	0
T36	0	255840	0	0
T37	0	249438	0	0
T38	0	175864	0	0
T39	0	170	0	0
T40	163776	0	0	0
T41	174478	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2566	0	0
T29	3800	72	0	0
T42	1106	1	0	0
T43	1379	19	0	0
T44	3358	42	0	0
T45	2300	9	0	0
T46	2796	15	0	0
T47	2317	9	0	0
T48	2305	15	0	0
T49	3423	63	0	0
T50	1743	8	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2330	0	0
T29	3800	39	0	0
T42	1106	11	0	0
T43	1379	10	0	0
T44	3358	73	0	0
T45	2300	7	0	0
T46	2796	41	0	0
T47	2317	17	0	0
T48	2305	16	0	0
T49	3423	62	0	0
T50	1743	5	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2321	0	0
T29	3800	33	0	0
T42	1106	23	0	0
T43	1379	8	0	0
T44	3358	65	0	0
T45	2300	7	0	0
T46	2796	23	0	0
T47	2317	12	0	0
T48	2305	24	0	0
T49	3423	80	0	0
T50	1743	8	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2245	0	0
T29	3800	42	0	0
T42	1106	9	0	0
T43	1379	6	0	0
T44	3358	25	0	0
T45	2300	8	0	0
T46	2796	37	0	0
T47	2317	6	0	0
T48	2305	13	0	0
T49	3423	51	0	0
T50	1743	11	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3084	0	0
T11	867038	0	0	0
T51	213573	5	0	0
T52	0	104	0	0
T53	0	27	0	0
T54	0	46	0	0
T55	0	4	0	0
T56	0	82	0	0
T57	0	70	0	0
T58	0	25	0	0
T59	0	58	0	0
T60	0	32	0	0
T61	159671	0	0	0
T62	277157	0	0	0
T63	920147	0	0	0
T64	928178	0	0	0
T65	517294	0	0	0
T66	630401	0	0	0
T67	189284	0	0	0
T68	575525	0	0	0