Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	72393463	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	74211090	1		T1	437978		T2	4408		T3	4341

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	145046815	1		T1	875796		T2	8611		T3	8582
values[0x0]	740586	1		T1	13		T2	8		T3	5
values[0x1]	817152	1		T1	17		T2	6		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57804549	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	88800004	1		T1	525820		T2	5292		T3	5157

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1355466	1		T1	3436		T2	33		T3	76
valid_sources[0x01]	424123	1		T1	3253		T2	42		T3	32
valid_sources[0x02]	422625	1		T1	3364		T2	14		T3	123
valid_sources[0x03]	422047	1		T1	3653		T2	35		T3	54
valid_sources[0x04]	423826	1		T1	3406		T2	39		T3	83
valid_sources[0x05]	5551554	1		T1	3410		T2	27		T3	77
valid_sources[0x06]	424735	1		T1	3416		T2	49		T3	57
valid_sources[0x07]	422211	1		T1	3313		T2	26		T3	59
valid_sources[0x08]	424683	1		T1	3469		T2	23		T3	100
valid_sources[0x09]	428780	1		T1	3103		T2	25		T3	14
valid_sources[0x0a]	428483	1		T1	3642		T2	35		T3	199
valid_sources[0x0b]	439917	1		T1	3562		T2	40		T4	23
valid_sources[0x0c]	2753943	1		T1	3306		T2	23		T3	14
valid_sources[0x0d]	426896	1		T1	3389		T2	50		T4	16
valid_sources[0x0e]	429467	1		T1	3382		T2	46		T3	11
valid_sources[0x0f]	421387	1		T1	3286		T2	35		T3	2
valid_sources[0x10]	424179	1		T1	3473		T2	21		T3	4
valid_sources[0x11]	501318	1		T1	3352		T2	30		T4	16
valid_sources[0x12]	496474	1		T1	3363		T2	44		T3	31
valid_sources[0x13]	424465	1		T1	3724		T2	41		T3	84
valid_sources[0x14]	425160	1		T1	3565		T2	34		T3	14
valid_sources[0x15]	423286	1		T1	3493		T2	41		T3	17
valid_sources[0x16]	440282	1		T1	3296		T2	34		T4	10
valid_sources[0x17]	428993	1		T1	3368		T2	25		T3	18
valid_sources[0x18]	420850	1		T1	3386		T2	36		T3	78
valid_sources[0x19]	702290	1		T1	3258		T2	40		T3	21
valid_sources[0x1a]	424815	1		T1	4127		T2	37		T3	87
valid_sources[0x1b]	423286	1		T1	3437		T2	33		T4	12
valid_sources[0x1c]	1171815	1		T1	3432		T2	25		T3	40
valid_sources[0x1d]	432509	1		T1	3381		T2	26		T4	17
valid_sources[0x1e]	426258	1		T1	3621		T2	25		T3	62
valid_sources[0x1f]	421412	1		T1	3335		T2	46		T4	11
valid_sources[0x20]	416262	1		T1	3178		T2	38		T3	129
valid_sources[0x21]	422744	1		T1	3236		T2	33		T3	253
valid_sources[0x22]	2599243	1		T1	3303		T2	39		T4	7
valid_sources[0x23]	425642	1		T1	3448		T2	27		T4	10
valid_sources[0x24]	422305	1		T1	3359		T2	33		T3	14
valid_sources[0x25]	626957	1		T1	3135		T2	24		T4	14
valid_sources[0x26]	473573	1		T1	3373		T2	29		T3	151
valid_sources[0x27]	420611	1		T1	3671		T2	30		T3	71
valid_sources[0x28]	426440	1		T1	3141		T2	30		T4	12
valid_sources[0x29]	422532	1		T1	3254		T2	40		T3	57
valid_sources[0x2a]	428457	1		T1	3549		T2	32		T4	5
valid_sources[0x2b]	429327	1		T1	3316		T2	46		T4	8
valid_sources[0x2c]	457326	1		T1	3799		T2	31		T4	10
valid_sources[0x2d]	553580	1		T1	3439		T2	30		T3	57
valid_sources[0x2e]	424858	1		T1	3305		T2	36		T4	13
valid_sources[0x2f]	427898	1		T1	3155		T2	47		T3	46
valid_sources[0x30]	480037	1		T1	3192		T2	41		T3	32
valid_sources[0x31]	648332	1		T1	3690		T2	26		T4	17
valid_sources[0x32]	424156	1		T1	3625		T2	40		T3	20
valid_sources[0x33]	426381	1		T1	3556		T2	44		T3	9
valid_sources[0x34]	423978	1		T1	3516		T2	35		T3	11
valid_sources[0x35]	435610	1		T1	3213		T2	36		T3	164
valid_sources[0x36]	424017	1		T1	3526		T2	28		T3	11
valid_sources[0x37]	940723	1		T1	3362		T2	30		T4	14
valid_sources[0x38]	424658	1		T1	3518		T2	28		T4	26
valid_sources[0x39]	425078	1		T1	3310		T2	37		T3	39
valid_sources[0x3a]	425428	1		T1	3672		T2	34		T3	12
valid_sources[0x3b]	424946	1		T1	3598		T2	29		T4	15
valid_sources[0x3c]	445430	1		T1	3236		T2	45		T3	16
valid_sources[0x3d]	426435	1		T1	3664		T2	26		T3	75
valid_sources[0x3e]	426059	1		T1	3357		T2	32		T3	42
valid_sources[0x3f]	424578	1		T1	3479		T2	37		T4	20
valid_sources[0x40]	424058	1		T1	3469		T2	20		T3	5
valid_sources[0x41]	420086	1		T1	3412		T2	48		T3	80
valid_sources[0x42]	426254	1		T1	3402		T2	32		T3	51
valid_sources[0x43]	1560214	1		T1	3540		T2	29		T3	22
valid_sources[0x44]	801700	1		T1	3581		T2	33		T4	14
valid_sources[0x45]	425397	1		T1	3645		T2	41		T3	16
valid_sources[0x46]	422011	1		T1	3627		T2	30		T4	11
valid_sources[0x47]	424744	1		T1	3485		T2	38		T3	68
valid_sources[0x48]	422299	1		T1	3327		T2	35		T3	94
valid_sources[0x49]	424426	1		T1	3393		T2	46		T3	25
valid_sources[0x4a]	499968	1		T1	3127		T2	36		T3	49
valid_sources[0x4b]	425081	1		T1	3784		T2	30		T3	6
valid_sources[0x4c]	421547	1		T1	3466		T2	34		T4	12
valid_sources[0x4d]	421156	1		T1	3754		T2	25		T3	29
valid_sources[0x4e]	456832	1		T1	3469		T2	38		T3	56
valid_sources[0x4f]	422366	1		T1	3464		T2	21		T4	9
valid_sources[0x50]	418698	1		T1	3253		T2	30		T3	49
valid_sources[0x51]	421479	1		T1	3583		T2	25		T3	34
valid_sources[0x52]	425576	1		T1	3477		T2	42		T3	39
valid_sources[0x53]	1003758	1		T1	3443		T2	37		T3	7
valid_sources[0x54]	425960	1		T1	3386		T2	44		T4	10
valid_sources[0x55]	424111	1		T1	3537		T2	38		T4	15
valid_sources[0x56]	421044	1		T1	3657		T2	27		T3	95
valid_sources[0x57]	426740	1		T1	3416		T2	41		T4	15
valid_sources[0x58]	431512	1		T1	3352		T2	37		T3	13
valid_sources[0x59]	422791	1		T1	3226		T2	30		T3	14
valid_sources[0x5a]	421748	1		T1	3360		T2	44		T3	51
valid_sources[0x5b]	554801	1		T1	3320		T2	28		T3	26
valid_sources[0x5c]	420192	1		T1	3407		T2	42		T3	100
valid_sources[0x5d]	422056	1		T1	3272		T2	57		T3	33
valid_sources[0x5e]	450722	1		T1	3382		T2	40		T3	36
valid_sources[0x5f]	421250	1		T1	3528		T2	25		T4	22
valid_sources[0x60]	463301	1		T1	3665		T2	28		T4	8
valid_sources[0x61]	3932498	1		T1	3363		T2	26		T4	11
valid_sources[0x62]	424290	1		T1	3257		T2	31		T3	181
valid_sources[0x63]	423500	1		T1	3488		T2	30		T3	67
valid_sources[0x64]	442229	1		T1	3316		T2	35		T4	16
valid_sources[0x65]	429691	1		T1	3372		T2	36		T3	59
valid_sources[0x66]	676309	1		T1	3399		T2	47		T3	73
valid_sources[0x67]	421757	1		T1	3484		T2	37		T4	10
valid_sources[0x68]	423892	1		T1	3516		T2	29		T3	22
valid_sources[0x69]	426733	1		T1	3478		T2	37		T3	5
valid_sources[0x6a]	421895	1		T1	3336		T2	28		T3	109
valid_sources[0x6b]	423910	1		T1	3519		T2	41		T3	9
valid_sources[0x6c]	460809	1		T1	3453		T2	28		T4	18
valid_sources[0x6d]	423544	1		T1	3459		T2	38		T3	108
valid_sources[0x6e]	551515	1		T1	3164		T2	41		T3	9
valid_sources[0x6f]	426900	1		T1	3334		T2	27		T3	3
valid_sources[0x70]	423879	1		T1	3554		T2	23		T4	10
valid_sources[0x71]	421261	1		T1	3502		T2	39		T3	98
valid_sources[0x72]	421816	1		T1	3437		T2	36		T3	6
valid_sources[0x73]	1267665	1		T1	3253		T2	25		T4	11
valid_sources[0x74]	424297	1		T1	3452		T2	47		T3	7
valid_sources[0x75]	424191	1		T1	3574		T2	44		T4	19
valid_sources[0x76]	423649	1		T1	3061		T2	23		T4	11
valid_sources[0x77]	420026	1		T1	3518		T2	35		T4	14
valid_sources[0x78]	423830	1		T1	3237		T2	44		T4	16
valid_sources[0x79]	420789	1		T1	3572		T2	38		T4	21
valid_sources[0x7a]	450561	1		T1	3554		T2	39		T3	4
valid_sources[0x7b]	792470	1		T1	3617		T2	30		T3	81
valid_sources[0x7c]	434938	1		T1	3559		T2	29		T3	36
valid_sources[0x7d]	426863	1		T1	3081		T2	39		T4	28
valid_sources[0x7e]	425820	1		T1	3551		T2	33		T4	12
valid_sources[0x7f]	424497	1		T1	3362		T2	33		T4	21
valid_sources[0x80]	421279	1		T1	3239		T2	35		T4	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72759290

1

T1

437958

T2

4399

T3

4335

values[0x0]

all_enables

biggest_size

727113

1

T1

10

T2

7

T3

3

values[0x1]

all_enables

biggest_size

724687

1

T1

10

T2

2

T3

3