Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2549814	0	0
cfg0_rd_A	2147483647	6743	0	0
compare_lower0_0_rd_A	2147483647	7137	0	0
compare_upper0_0_rd_A	2147483647	6814	0	0
ctrl_rd_A	2147483647	6469	0	0
intr_enable0_rd_A	2147483647	9206	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2549814	0	0
T16	698365	212336	0	0
T17	160701	41049	0	0
T18	0	60430	0	0
T40	670968	0	0	0
T41	0	151843	0	0
T42	0	36141	0	0
T43	0	42004	0	0
T44	0	217712	0	0
T45	0	176439	0	0
T46	0	65236	0	0
T47	0	161911	0	0
T48	416076	0	0	0
T49	100872	0	0	0
T50	515109	0	0	0
T51	893299	0	0	0
T52	646419	0	0	0
T53	287813	0	0	0
T54	203672	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6743	0	0
T17	160701	380	0	0
T34	0	67	0	0
T39	0	22	0	0
T42	0	338	0	0
T55	0	3697	0	0
T56	0	670	0	0
T57	0	24	0	0
T58	0	4	0	0
T59	0	12	0	0
T60	0	67	0	0
T61	416850	0	0	0
T62	442608	0	0	0
T63	390832	0	0	0
T64	117903	0	0	0
T65	686868	0	0	0
T66	467073	0	0	0
T67	520454	0	0	0
T68	167450	0	0	0
T69	456278	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7137	0	0
T17	160701	405	0	0
T34	0	43	0	0
T39	0	54	0	0
T42	0	452	0	0
T55	0	3817	0	0
T56	0	855	0	0
T57	0	30	0	0
T58	0	10	0	0
T59	0	13	0	0
T60	0	74	0	0
T61	416850	0	0	0
T62	442608	0	0	0
T63	390832	0	0	0
T64	117903	0	0	0
T65	686868	0	0	0
T66	467073	0	0	0
T67	520454	0	0	0
T68	167450	0	0	0
T69	456278	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6814	0	0
T17	160701	368	0	0
T34	0	37	0	0
T39	0	54	0	0
T42	0	447	0	0
T55	0	3578	0	0
T56	0	728	0	0
T57	0	20	0	0
T59	0	11	0	0
T60	0	79	0	0
T61	416850	0	0	0
T62	442608	0	0	0
T63	390832	0	0	0
T64	117903	0	0	0
T65	686868	0	0	0
T66	467073	0	0	0
T67	520454	0	0	0
T68	167450	0	0	0
T69	456278	0	0	0
T70	0	3	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6469	0	0
T17	160701	479	0	0
T34	0	44	0	0
T39	0	68	0	0
T42	0	363	0	0
T55	0	3226	0	0
T56	0	785	0	0
T57	0	21	0	0
T58	0	5	0	0
T59	0	14	0	0
T61	416850	0	0	0
T62	442608	0	0	0
T63	390832	0	0	0
T64	117903	0	0	0
T65	686868	0	0	0
T66	467073	0	0	0
T67	520454	0	0	0
T68	167450	0	0	0
T69	456278	0	0	0
T71	0	6	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9206	0	0
T17	160701	447	0	0
T31	0	118	0	0
T42	0	579	0	0
T50	515109	23	0	0
T51	893299	0	0	0
T52	646419	0	0	0
T53	287813	0	0	0
T54	203672	0	0	0
T61	416850	0	0	0
T62	442608	0	0	0
T63	390832	0	0	0
T64	117903	0	0	0
T72	0	126	0	0
T73	0	28	0	0
T74	0	15	0	0
T75	0	15	0	0
T76	0	33	0	0
T77	0	110	0	0