Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2576868	0	0
cfg0_rd_A	2147483647	13478	0	0
compare_lower0_0_rd_A	2147483647	14742	0	0
compare_upper0_0_rd_A	2147483647	12964	0	0
ctrl_rd_A	2147483647	12722	0	0
intr_enable0_rd_A	2147483647	15598	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2576868	0	0
T11	540328	152628	0	0
T12	0	74030	0	0
T13	0	95790	0	0
T20	0	154140	0	0
T34	0	163612	0	0
T35	0	198346	0	0
T36	0	85002	0	0
T37	0	352895	0	0
T38	0	180052	0	0
T39	0	303239	0	0
T40	382928	0	0	0
T41	283313	0	0	0
T42	520195	0	0	0
T43	413965	0	0	0
T44	346735	0	0	0
T45	557403	0	0	0
T46	125151	0	0	0
T47	16034	0	0	0
T48	140663	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13478	0	0
T11	540328	895	0	0
T13	0	933	0	0
T20	0	1590	0	0
T34	0	877	0	0
T39	0	3099	0	0
T40	382928	0	0	0
T41	283313	0	0	0
T42	520195	0	0	0
T43	413965	0	0	0
T44	346735	0	0	0
T45	557403	0	0	0
T46	125151	0	0	0
T47	16034	0	0	0
T48	140663	0	0	0
T49	0	857	0	0
T50	0	816	0	0
T51	0	2174	0	0
T52	0	45	0	0
T53	0	17	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14742	0	0
T11	540328	1024	0	0
T13	0	1035	0	0
T20	0	1900	0	0
T34	0	884	0	0
T39	0	3509	0	0
T40	382928	0	0	0
T41	283313	0	0	0
T42	520195	0	0	0
T43	413965	0	0	0
T44	346735	0	0	0
T45	557403	0	0	0
T46	125151	0	0	0
T47	16034	0	0	0
T48	140663	0	0	0
T49	0	1156	0	0
T50	0	987	0	0
T51	0	2434	0	0
T52	0	30	0	0
T53	0	1	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12964	0	0
T11	540328	894	0	0
T13	0	961	0	0
T20	0	1530	0	0
T34	0	945	0	0
T39	0	3071	0	0
T40	382928	0	0	0
T41	283313	0	0	0
T42	520195	0	0	0
T43	413965	0	0	0
T44	346735	0	0	0
T45	557403	0	0	0
T46	125151	0	0	0
T47	16034	0	0	0
T48	140663	0	0	0
T49	0	801	0	0
T50	0	816	0	0
T51	0	2170	0	0
T52	0	24	0	0
T53	0	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12722	0	0
T11	540328	803	0	0
T13	0	924	0	0
T20	0	1391	0	0
T34	0	734	0	0
T39	0	3041	0	0
T40	382928	0	0	0
T41	283313	0	0	0
T42	520195	0	0	0
T43	413965	0	0	0
T44	346735	0	0	0
T45	557403	0	0	0
T46	125151	0	0	0
T47	16034	0	0	0
T48	140663	0	0	0
T49	0	894	0	0
T50	0	848	0	0
T51	0	2372	0	0
T52	0	17	0	0
T53	0	13	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15598	0	0
T2	568157	119	0	0
T3	454483	0	0	0
T4	155534	0	0	0
T5	150138	0	0	0
T6	466403	0	0	0
T7	350778	0	0	0
T8	271026	0	0	0
T9	438798	0	0	0
T10	161410	0	0	0
T11	540328	858	0	0
T13	0	1232	0	0
T20	0	1746	0	0
T34	0	1106	0	0
T54	0	87	0	0
T55	0	28	0	0
T56	0	34	0	0
T57	0	41	0	0
T58	0	60	0	0