Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 579
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T509 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.994988481 Jul 18 04:42:13 PM PDT 24 Jul 18 04:42:17 PM PDT 24 89107506 ps
T510 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.539919585 Jul 18 04:42:11 PM PDT 24 Jul 18 04:42:15 PM PDT 24 54752146 ps
T511 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.328987920 Jul 18 04:42:08 PM PDT 24 Jul 18 04:42:12 PM PDT 24 38652612 ps
T512 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1267606847 Jul 18 04:41:54 PM PDT 24 Jul 18 04:41:58 PM PDT 24 87633589 ps
T88 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1263930408 Jul 18 04:41:43 PM PDT 24 Jul 18 04:41:45 PM PDT 24 13047501 ps
T513 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2457718279 Jul 18 04:41:56 PM PDT 24 Jul 18 04:42:01 PM PDT 24 67813819 ps
T514 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1199016062 Jul 18 04:42:16 PM PDT 24 Jul 18 04:42:20 PM PDT 24 18126593 ps
T515 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.303197878 Jul 18 04:42:11 PM PDT 24 Jul 18 04:42:15 PM PDT 24 122170755 ps
T516 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2555906606 Jul 18 04:42:15 PM PDT 24 Jul 18 04:42:19 PM PDT 24 17199680 ps
T517 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2339846838 Jul 18 04:41:50 PM PDT 24 Jul 18 04:41:52 PM PDT 24 18771736 ps
T518 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1258338099 Jul 18 04:41:52 PM PDT 24 Jul 18 04:41:56 PM PDT 24 17883476 ps
T519 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1727459481 Jul 18 04:41:48 PM PDT 24 Jul 18 04:41:50 PM PDT 24 19985767 ps
T520 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1453070058 Jul 18 04:41:56 PM PDT 24 Jul 18 04:42:02 PM PDT 24 33012761 ps
T521 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3381330267 Jul 18 04:41:37 PM PDT 24 Jul 18 04:41:39 PM PDT 24 248198568 ps
T522 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.19178006 Jul 18 04:41:52 PM PDT 24 Jul 18 04:41:56 PM PDT 24 79395949 ps
T523 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.716360752 Jul 18 04:41:39 PM PDT 24 Jul 18 04:41:41 PM PDT 24 17554118 ps
T89 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1692052354 Jul 18 04:41:38 PM PDT 24 Jul 18 04:41:40 PM PDT 24 21839254 ps
T524 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1602502864 Jul 18 04:42:03 PM PDT 24 Jul 18 04:42:07 PM PDT 24 31868955 ps
T525 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1409676489 Jul 18 04:42:07 PM PDT 24 Jul 18 04:42:11 PM PDT 24 20395327 ps
T526 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4248614941 Jul 18 04:42:15 PM PDT 24 Jul 18 04:42:19 PM PDT 24 27054262 ps
T527 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3251585310 Jul 18 04:41:43 PM PDT 24 Jul 18 04:41:45 PM PDT 24 12424520 ps
T528 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3355727526 Jul 18 04:42:06 PM PDT 24 Jul 18 04:42:11 PM PDT 24 47073789 ps
T529 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.120979025 Jul 18 04:42:01 PM PDT 24 Jul 18 04:42:05 PM PDT 24 54555720 ps
T530 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1670341791 Jul 18 04:42:05 PM PDT 24 Jul 18 04:42:10 PM PDT 24 33594915 ps
T531 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3900062086 Jul 18 04:42:02 PM PDT 24 Jul 18 04:42:07 PM PDT 24 118132920 ps
T91 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1389129973 Jul 18 04:41:46 PM PDT 24 Jul 18 04:41:49 PM PDT 24 36330765 ps
T532 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.353029154 Jul 18 04:41:55 PM PDT 24 Jul 18 04:42:01 PM PDT 24 544611705 ps
T533 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1912242285 Jul 18 04:41:58 PM PDT 24 Jul 18 04:42:05 PM PDT 24 164250193 ps
T534 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2373384317 Jul 18 04:41:38 PM PDT 24 Jul 18 04:41:42 PM PDT 24 140380074 ps
T535 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1606425795 Jul 18 04:41:43 PM PDT 24 Jul 18 04:41:45 PM PDT 24 19034853 ps
T536 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.644960343 Jul 18 04:42:00 PM PDT 24 Jul 18 04:42:07 PM PDT 24 499138137 ps
T537 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1512210835 Jul 18 04:42:13 PM PDT 24 Jul 18 04:42:17 PM PDT 24 39402885 ps
T538 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3156216071 Jul 18 04:42:10 PM PDT 24 Jul 18 04:42:14 PM PDT 24 21393746 ps
T539 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.456143450 Jul 18 04:41:52 PM PDT 24 Jul 18 04:41:55 PM PDT 24 18286290 ps
T540 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1201620154 Jul 18 04:42:09 PM PDT 24 Jul 18 04:42:12 PM PDT 24 24836991 ps
T541 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1271593020 Jul 18 04:41:39 PM PDT 24 Jul 18 04:41:41 PM PDT 24 33920871 ps
T542 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2983351118 Jul 18 04:42:14 PM PDT 24 Jul 18 04:42:18 PM PDT 24 12993663 ps
T543 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3296562568 Jul 18 04:42:16 PM PDT 24 Jul 18 04:42:20 PM PDT 24 59654985 ps
T544 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4294925089 Jul 18 04:42:00 PM PDT 24 Jul 18 04:42:05 PM PDT 24 23661139 ps
T545 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3143184379 Jul 18 04:41:38 PM PDT 24 Jul 18 04:41:41 PM PDT 24 16937254 ps
T546 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2633783399 Jul 18 04:42:06 PM PDT 24 Jul 18 04:42:11 PM PDT 24 192768933 ps
T109 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3338564777 Jul 18 04:41:52 PM PDT 24 Jul 18 04:41:56 PM PDT 24 142465779 ps
T547 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2018941096 Jul 18 04:42:19 PM PDT 24 Jul 18 04:42:22 PM PDT 24 44795260 ps
T110 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3484811620 Jul 18 04:41:51 PM PDT 24 Jul 18 04:41:53 PM PDT 24 494433916 ps
T548 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2118208366 Jul 18 04:41:58 PM PDT 24 Jul 18 04:42:03 PM PDT 24 58952483 ps
T549 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.991499707 Jul 18 04:41:55 PM PDT 24 Jul 18 04:41:59 PM PDT 24 217093322 ps
T90 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1042928698 Jul 18 04:41:56 PM PDT 24 Jul 18 04:42:01 PM PDT 24 12982762 ps
T550 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2873933188 Jul 18 04:42:16 PM PDT 24 Jul 18 04:42:20 PM PDT 24 44723964 ps
T551 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.849483643 Jul 18 04:42:01 PM PDT 24 Jul 18 04:42:06 PM PDT 24 56566812 ps
T552 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3064873931 Jul 18 04:42:17 PM PDT 24 Jul 18 04:42:21 PM PDT 24 71355523 ps
T553 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1865010807 Jul 18 04:42:20 PM PDT 24 Jul 18 04:42:23 PM PDT 24 15283134 ps
T554 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3796270369 Jul 18 04:41:51 PM PDT 24 Jul 18 04:41:53 PM PDT 24 43734083 ps
T92 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1870503989 Jul 18 04:41:44 PM PDT 24 Jul 18 04:41:46 PM PDT 24 41081224 ps
T93 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3176581464 Jul 18 04:41:56 PM PDT 24 Jul 18 04:42:01 PM PDT 24 14459427 ps
T555 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1286660448 Jul 18 04:42:00 PM PDT 24 Jul 18 04:42:05 PM PDT 24 79776615 ps
T556 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.48977254 Jul 18 04:41:41 PM PDT 24 Jul 18 04:41:44 PM PDT 24 25308454 ps
T557 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.990441699 Jul 18 04:42:17 PM PDT 24 Jul 18 04:42:21 PM PDT 24 48044411 ps
T558 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2414932122 Jul 18 04:41:44 PM PDT 24 Jul 18 04:41:46 PM PDT 24 25954287 ps
T559 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3726193316 Jul 18 04:41:56 PM PDT 24 Jul 18 04:42:01 PM PDT 24 114269532 ps
T560 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1986720694 Jul 18 04:41:54 PM PDT 24 Jul 18 04:41:58 PM PDT 24 10972240 ps
T561 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.4185077204 Jul 18 04:42:12 PM PDT 24 Jul 18 04:42:16 PM PDT 24 47874747 ps
T562 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2592816528 Jul 18 04:41:55 PM PDT 24 Jul 18 04:42:00 PM PDT 24 23031718 ps
T563 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.61695958 Jul 18 04:41:51 PM PDT 24 Jul 18 04:41:54 PM PDT 24 142662768 ps
T564 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2281899370 Jul 18 04:41:56 PM PDT 24 Jul 18 04:42:01 PM PDT 24 36270000 ps
T565 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2423837139 Jul 18 04:41:53 PM PDT 24 Jul 18 04:41:57 PM PDT 24 18541644 ps
T566 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1861360508 Jul 18 04:41:56 PM PDT 24 Jul 18 04:42:01 PM PDT 24 46578195 ps
T567 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1596041521 Jul 18 04:50:27 PM PDT 24 Jul 18 04:50:28 PM PDT 24 34913226 ps
T568 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3686672720 Jul 18 04:42:16 PM PDT 24 Jul 18 04:42:19 PM PDT 24 13263796 ps
T569 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1543203242 Jul 18 04:42:05 PM PDT 24 Jul 18 04:42:11 PM PDT 24 474682388 ps
T570 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3966803480 Jul 18 04:41:41 PM PDT 24 Jul 18 04:41:44 PM PDT 24 147441234 ps
T571 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1776425768 Jul 18 04:42:11 PM PDT 24 Jul 18 04:42:14 PM PDT 24 11735421 ps
T572 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2275254548 Jul 18 04:42:20 PM PDT 24 Jul 18 04:42:23 PM PDT 24 37630043 ps
T573 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3274839835 Jul 18 04:42:16 PM PDT 24 Jul 18 04:42:19 PM PDT 24 91203063 ps
T574 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.588459602 Jul 18 04:41:58 PM PDT 24 Jul 18 04:42:04 PM PDT 24 47358358 ps
T575 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1994315672 Jul 18 04:41:56 PM PDT 24 Jul 18 04:42:01 PM PDT 24 106626083 ps
T576 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1122995165 Jul 18 04:41:52 PM PDT 24 Jul 18 04:41:55 PM PDT 24 32453635 ps
T577 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2540024245 Jul 18 04:42:16 PM PDT 24 Jul 18 04:42:20 PM PDT 24 30119379 ps
T578 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.996135676 Jul 18 04:41:57 PM PDT 24 Jul 18 04:42:02 PM PDT 24 49133779 ps
T579 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1272117944 Jul 18 04:41:56 PM PDT 24 Jul 18 04:42:02 PM PDT 24 35579125 ps

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.3203223062
Short name T7
Test name
Test status
Simulation time 41162229606 ps
CPU time 318.85 seconds
Started Jul 18 04:43:13 PM PDT 24
Finished Jul 18 04:48:34 PM PDT 24
Peak memory 206256 kb
Host smart-bf103d3b-bb0f-444b-a457-e54a25d1e73d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203223062 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.3203223062
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/197.rv_timer_random.328759000
Short name T4
Test name
Test status
Simulation time 67598414791 ps
CPU time 349.4 seconds
Started Jul 18 04:43:43 PM PDT 24
Finished Jul 18 04:49:33 PM PDT 24
Peak memory 191544 kb
Host smart-bb54e252-360c-4ad2-92fb-f2bb4d702995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328759000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.328759000
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2314325934
Short name T20
Test name
Test status
Simulation time 953562171243 ps
CPU time 1459.22 seconds
Started Jul 18 04:42:29 PM PDT 24
Finished Jul 18 05:06:50 PM PDT 24
Peak memory 191580 kb
Host smart-9e502c5c-8b06-4a2d-8d52-ebf972924f55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314325934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2314325934
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1704110217
Short name T29
Test name
Test status
Simulation time 91741739 ps
CPU time 1.07 seconds
Started Jul 18 04:42:01 PM PDT 24
Finished Jul 18 04:42:06 PM PDT 24
Peak memory 194668 kb
Host smart-90495286-2889-4677-ba99-156bc5b538a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704110217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1704110217
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3384695615
Short name T62
Test name
Test status
Simulation time 3771027079220 ps
CPU time 1510.3 seconds
Started Jul 18 04:42:55 PM PDT 24
Finished Jul 18 05:08:07 PM PDT 24
Peak memory 191572 kb
Host smart-782f675d-1a02-429c-b346-5c501e468891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384695615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3384695615
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3190796726
Short name T211
Test name
Test status
Simulation time 635100928675 ps
CPU time 3057.89 seconds
Started Jul 18 04:42:48 PM PDT 24
Finished Jul 18 05:33:50 PM PDT 24
Peak memory 196400 kb
Host smart-79b0201a-85e1-40f0-9628-cf3647b42f65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190796726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3190796726
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2248159271
Short name T59
Test name
Test status
Simulation time 1810712191089 ps
CPU time 1684.45 seconds
Started Jul 18 04:43:33 PM PDT 24
Finished Jul 18 05:11:41 PM PDT 24
Peak memory 191564 kb
Host smart-29c16fb0-3eba-48d0-8411-54868c0bfcbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248159271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2248159271
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3212150398
Short name T64
Test name
Test status
Simulation time 2207394859189 ps
CPU time 1158.8 seconds
Started Jul 18 04:43:08 PM PDT 24
Finished Jul 18 05:02:28 PM PDT 24
Peak memory 196748 kb
Host smart-478ce68f-5b39-490e-983a-9f34819fbb36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212150398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3212150398
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1960438764
Short name T14
Test name
Test status
Simulation time 234995429 ps
CPU time 0.86 seconds
Started Jul 18 04:42:30 PM PDT 24
Finished Jul 18 04:42:33 PM PDT 24
Peak memory 213700 kb
Host smart-d425e82b-501e-49ba-9f41-2ce4378a2d25
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960438764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1960438764
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1541930613
Short name T236
Test name
Test status
Simulation time 568557933835 ps
CPU time 1858.3 seconds
Started Jul 18 04:43:33 PM PDT 24
Finished Jul 18 05:14:35 PM PDT 24
Peak memory 191564 kb
Host smart-eb831d1a-10e1-4246-9623-b05bc7b7940d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541930613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1541930613
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.52145979
Short name T154
Test name
Test status
Simulation time 1658430593454 ps
CPU time 986.72 seconds
Started Jul 18 04:43:23 PM PDT 24
Finished Jul 18 04:59:52 PM PDT 24
Peak memory 191596 kb
Host smart-0a9d4dd5-c159-4cbd-b33b-499ffc1c5929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52145979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.52145979
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.2860460257
Short name T37
Test name
Test status
Simulation time 98352363130 ps
CPU time 996.61 seconds
Started Jul 18 04:42:33 PM PDT 24
Finished Jul 18 04:59:11 PM PDT 24
Peak memory 210496 kb
Host smart-64ef72b8-cba3-45dd-bf3c-a3f02639e74e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860460257 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.2860460257
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.rv_timer_random.409963483
Short name T112
Test name
Test status
Simulation time 567211542219 ps
CPU time 669.42 seconds
Started Jul 18 04:43:28 PM PDT 24
Finished Jul 18 04:54:40 PM PDT 24
Peak memory 191552 kb
Host smart-4e48c828-71a2-4402-bc2c-f525c8450862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409963483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.409963483
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2295235309
Short name T158
Test name
Test status
Simulation time 978081678866 ps
CPU time 5591.99 seconds
Started Jul 18 04:42:40 PM PDT 24
Finished Jul 18 06:15:55 PM PDT 24
Peak memory 196300 kb
Host smart-fa212392-3e62-441d-812d-ad7f7bf5ed5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295235309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2295235309
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.944130976
Short name T290
Test name
Test status
Simulation time 1402026732985 ps
CPU time 3191.13 seconds
Started Jul 18 04:42:46 PM PDT 24
Finished Jul 18 05:35:59 PM PDT 24
Peak memory 196412 kb
Host smart-b5a7831f-ebf4-48ae-b01e-373e8d463816
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944130976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
944130976
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2611545879
Short name T114
Test name
Test status
Simulation time 7714293346934 ps
CPU time 3131.85 seconds
Started Jul 18 04:42:32 PM PDT 24
Finished Jul 18 05:34:46 PM PDT 24
Peak memory 191668 kb
Host smart-23dfc185-5169-4423-97a3-514a76ba011d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611545879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2611545879
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.4122584675
Short name T65
Test name
Test status
Simulation time 2916773716976 ps
CPU time 1886.82 seconds
Started Jul 18 04:42:35 PM PDT 24
Finished Jul 18 05:14:03 PM PDT 24
Peak memory 191580 kb
Host smart-cf5f654e-b14c-4af6-9ec1-8c04904e8447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122584675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.4122584675
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3752680558
Short name T192
Test name
Test status
Simulation time 1290689101359 ps
CPU time 847.84 seconds
Started Jul 18 04:43:27 PM PDT 24
Finished Jul 18 04:57:38 PM PDT 24
Peak memory 191544 kb
Host smart-d5beb897-6276-4d20-9a8d-eebfcc97de9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752680558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3752680558
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_random.3083884082
Short name T99
Test name
Test status
Simulation time 2945060818793 ps
CPU time 624.53 seconds
Started Jul 18 04:42:19 PM PDT 24
Finished Jul 18 04:52:46 PM PDT 24
Peak memory 191564 kb
Host smart-2c413726-13f6-4d8c-97e0-f1e9ef28ca78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083884082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3083884082
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.3965022102
Short name T218
Test name
Test status
Simulation time 199322497263 ps
CPU time 1862.42 seconds
Started Jul 18 04:42:39 PM PDT 24
Finished Jul 18 05:13:44 PM PDT 24
Peak memory 191564 kb
Host smart-d82d7efe-a73a-4023-b6c1-b154081a94c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965022102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3965022102
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1521500153
Short name T149
Test name
Test status
Simulation time 319976141639 ps
CPU time 382.71 seconds
Started Jul 18 04:43:41 PM PDT 24
Finished Jul 18 04:50:04 PM PDT 24
Peak memory 191592 kb
Host smart-c37266dc-2307-46b2-9156-a556fa922245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521500153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1521500153
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3811334826
Short name T85
Test name
Test status
Simulation time 29975214 ps
CPU time 0.63 seconds
Started Jul 18 04:42:01 PM PDT 24
Finished Jul 18 04:42:05 PM PDT 24
Peak memory 182368 kb
Host smart-7ce9bbbb-e2a6-49e8-827e-961e81e2804d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811334826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3811334826
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.471693289
Short name T261
Test name
Test status
Simulation time 219559197779 ps
CPU time 698.86 seconds
Started Jul 18 04:42:15 PM PDT 24
Finished Jul 18 04:53:57 PM PDT 24
Peak memory 191552 kb
Host smart-c3f76dc3-eeef-4514-8832-bc1411f9fbaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471693289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.471693289
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/106.rv_timer_random.3464149607
Short name T172
Test name
Test status
Simulation time 835141056714 ps
CPU time 594.06 seconds
Started Jul 18 04:43:27 PM PDT 24
Finished Jul 18 04:53:24 PM PDT 24
Peak memory 191600 kb
Host smart-8ec6452d-b4fb-412b-8380-3bfcd21d94aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464149607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3464149607
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.2276373977
Short name T43
Test name
Test status
Simulation time 90997145246 ps
CPU time 527.2 seconds
Started Jul 18 04:43:31 PM PDT 24
Finished Jul 18 04:52:21 PM PDT 24
Peak memory 191668 kb
Host smart-b887ef33-0be2-4459-a61e-7b15cac5dd8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276373977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2276373977
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3187178943
Short name T74
Test name
Test status
Simulation time 810684140089 ps
CPU time 2646.61 seconds
Started Jul 18 04:43:43 PM PDT 24
Finished Jul 18 05:27:51 PM PDT 24
Peak memory 191952 kb
Host smart-7df5a8ee-8273-4c81-be64-e23f29e49a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187178943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3187178943
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3446248750
Short name T66
Test name
Test status
Simulation time 2884138739409 ps
CPU time 1199.32 seconds
Started Jul 18 04:42:50 PM PDT 24
Finished Jul 18 05:02:51 PM PDT 24
Peak memory 191600 kb
Host smart-7ac82c61-60fb-43ee-afcc-8fd618372454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446248750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3446248750
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.79537639
Short name T255
Test name
Test status
Simulation time 3297920553380 ps
CPU time 1372.8 seconds
Started Jul 18 04:43:10 PM PDT 24
Finished Jul 18 05:06:05 PM PDT 24
Peak memory 183504 kb
Host smart-20cc74d4-d03b-4759-9c45-82b2ce5179e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79537639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.rv_timer_cfg_update_on_fly.79537639
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/56.rv_timer_random.2373613827
Short name T182
Test name
Test status
Simulation time 159599955256 ps
CPU time 3487.42 seconds
Started Jul 18 04:43:26 PM PDT 24
Finished Jul 18 05:41:37 PM PDT 24
Peak memory 191556 kb
Host smart-971e15e1-550b-49e8-a10b-da4dfe258194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373613827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2373613827
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.4011961258
Short name T122
Test name
Test status
Simulation time 204259408094 ps
CPU time 209.52 seconds
Started Jul 18 04:43:28 PM PDT 24
Finished Jul 18 04:47:01 PM PDT 24
Peak memory 190796 kb
Host smart-20ec3ee5-1014-471b-a1e3-cad978b33500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011961258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.4011961258
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random.3586800356
Short name T170
Test name
Test status
Simulation time 507037407878 ps
CPU time 389.75 seconds
Started Jul 18 04:42:44 PM PDT 24
Finished Jul 18 04:49:16 PM PDT 24
Peak memory 191600 kb
Host smart-7986dc0f-5abb-43e6-98fa-def09df4aeac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586800356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3586800356
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.4283868171
Short name T102
Test name
Test status
Simulation time 554230217650 ps
CPU time 835.14 seconds
Started Jul 18 04:43:06 PM PDT 24
Finished Jul 18 04:57:02 PM PDT 24
Peak memory 191692 kb
Host smart-5f98dd7e-d0f3-4c2b-a575-e18c9f14f728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283868171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.4283868171
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_random.3334673270
Short name T52
Test name
Test status
Simulation time 2243306566630 ps
CPU time 730.55 seconds
Started Jul 18 04:42:32 PM PDT 24
Finished Jul 18 04:54:44 PM PDT 24
Peak memory 191460 kb
Host smart-31b92dac-0576-49de-816f-c111f70fb562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334673270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3334673270
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3959809746
Short name T207
Test name
Test status
Simulation time 652440611354 ps
CPU time 543.58 seconds
Started Jul 18 04:43:17 PM PDT 24
Finished Jul 18 04:52:22 PM PDT 24
Peak memory 191888 kb
Host smart-041cf8bf-27d5-4b01-80ff-fbe22ed95ec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959809746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3959809746
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2529874686
Short name T286
Test name
Test status
Simulation time 391695681420 ps
CPU time 187.63 seconds
Started Jul 18 04:43:27 PM PDT 24
Finished Jul 18 04:46:38 PM PDT 24
Peak memory 195172 kb
Host smart-bbf07e26-7c0d-4486-b1a8-b4490063eb20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529874686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2529874686
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2326837992
Short name T199
Test name
Test status
Simulation time 158592296385 ps
CPU time 498.43 seconds
Started Jul 18 04:43:34 PM PDT 24
Finished Jul 18 04:51:56 PM PDT 24
Peak memory 191676 kb
Host smart-bb41702f-e662-4b37-9f1e-65262831a2b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326837992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2326837992
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.1754602350
Short name T263
Test name
Test status
Simulation time 819047665714 ps
CPU time 435.68 seconds
Started Jul 18 04:43:41 PM PDT 24
Finished Jul 18 04:50:58 PM PDT 24
Peak memory 191564 kb
Host smart-fc3ac94e-daa0-4062-8d99-09f0b138b495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754602350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1754602350
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2325518163
Short name T165
Test name
Test status
Simulation time 548118507754 ps
CPU time 356 seconds
Started Jul 18 04:43:47 PM PDT 24
Finished Jul 18 04:49:46 PM PDT 24
Peak memory 195256 kb
Host smart-31cd9866-a329-4f66-81a4-81383093581a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325518163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2325518163
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.4127307884
Short name T128
Test name
Test status
Simulation time 440480829393 ps
CPU time 226.86 seconds
Started Jul 18 04:43:48 PM PDT 24
Finished Jul 18 04:47:38 PM PDT 24
Peak memory 191952 kb
Host smart-73cb4879-ae9b-4470-8755-9c36d362cabe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127307884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.4127307884
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.4062905900
Short name T271
Test name
Test status
Simulation time 288617326355 ps
CPU time 728.85 seconds
Started Jul 18 04:42:42 PM PDT 24
Finished Jul 18 04:54:53 PM PDT 24
Peak memory 191956 kb
Host smart-2aba86b3-8aba-475a-aa86-8ce51206f78e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062905900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.4062905900
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/83.rv_timer_random.4014309594
Short name T151
Test name
Test status
Simulation time 107159189535 ps
CPU time 177.36 seconds
Started Jul 18 04:43:33 PM PDT 24
Finished Jul 18 04:46:34 PM PDT 24
Peak memory 191544 kb
Host smart-cd4376ca-fd76-4b93-9dda-c296de70dafd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014309594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.4014309594
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1077328933
Short name T138
Test name
Test status
Simulation time 745687938425 ps
CPU time 267.26 seconds
Started Jul 18 04:43:28 PM PDT 24
Finished Jul 18 04:47:58 PM PDT 24
Peak memory 191664 kb
Host smart-042b24ca-7019-40b8-a112-e0500c72c671
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077328933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1077328933
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.798376634
Short name T72
Test name
Test status
Simulation time 137542354794 ps
CPU time 530.5 seconds
Started Jul 18 04:43:24 PM PDT 24
Finished Jul 18 04:52:18 PM PDT 24
Peak memory 191556 kb
Host smart-f1c474b2-5c52-459f-a914-0218e81b81d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798376634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.798376634
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.557074826
Short name T223
Test name
Test status
Simulation time 108025391751 ps
CPU time 554.2 seconds
Started Jul 18 04:43:50 PM PDT 24
Finished Jul 18 04:53:07 PM PDT 24
Peak memory 191616 kb
Host smart-91f279c3-783a-4eec-95c7-feca5d5950c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557074826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.557074826
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2836567990
Short name T56
Test name
Test status
Simulation time 1056634171077 ps
CPU time 1886.44 seconds
Started Jul 18 04:43:41 PM PDT 24
Finished Jul 18 05:15:09 PM PDT 24
Peak memory 191536 kb
Host smart-cb294c82-f71b-4c27-83b6-428141249a1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836567990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2836567990
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.3238886002
Short name T193
Test name
Test status
Simulation time 500341850083 ps
CPU time 506.52 seconds
Started Jul 18 04:43:39 PM PDT 24
Finished Jul 18 04:52:07 PM PDT 24
Peak memory 191560 kb
Host smart-51366dc7-7b14-49bf-a073-adbb00b45934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238886002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3238886002
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2793833359
Short name T234
Test name
Test status
Simulation time 379709027413 ps
CPU time 1312.77 seconds
Started Jul 18 04:42:45 PM PDT 24
Finished Jul 18 05:04:40 PM PDT 24
Peak memory 191556 kb
Host smart-85d4c6e3-836c-4c9b-89b2-d5eb2d2495f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793833359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2793833359
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/86.rv_timer_random.530888669
Short name T442
Test name
Test status
Simulation time 106207944581 ps
CPU time 170.25 seconds
Started Jul 18 04:43:41 PM PDT 24
Finished Jul 18 04:46:33 PM PDT 24
Peak memory 191548 kb
Host smart-79c648a7-6e86-4e9b-a53e-b818003a25b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530888669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.530888669
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1665410138
Short name T281
Test name
Test status
Simulation time 273901346713 ps
CPU time 645.43 seconds
Started Jul 18 04:43:34 PM PDT 24
Finished Jul 18 04:54:22 PM PDT 24
Peak memory 191580 kb
Host smart-402d482a-f6cc-411b-9378-690b644793ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665410138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1665410138
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2713885560
Short name T51
Test name
Test status
Simulation time 313280971616 ps
CPU time 521.09 seconds
Started Jul 18 04:43:28 PM PDT 24
Finished Jul 18 04:52:12 PM PDT 24
Peak memory 195076 kb
Host smart-7bddb5da-dbde-4bf1-abcb-ca732692edc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713885560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2713885560
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.277794575
Short name T176
Test name
Test status
Simulation time 195233892007 ps
CPU time 336.51 seconds
Started Jul 18 04:43:28 PM PDT 24
Finished Jul 18 04:49:07 PM PDT 24
Peak memory 191664 kb
Host smart-442d6835-5213-4651-b6d5-4f271fb12bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277794575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.277794575
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2285379855
Short name T277
Test name
Test status
Simulation time 3306434226661 ps
CPU time 1294.77 seconds
Started Jul 18 04:42:36 PM PDT 24
Finished Jul 18 05:04:12 PM PDT 24
Peak memory 183768 kb
Host smart-e8e13d86-32cb-4a1c-9449-9e25e692fe89
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285379855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2285379855
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/142.rv_timer_random.2371230534
Short name T338
Test name
Test status
Simulation time 106836144797 ps
CPU time 257.82 seconds
Started Jul 18 04:43:33 PM PDT 24
Finished Jul 18 04:47:54 PM PDT 24
Peak memory 191556 kb
Host smart-f6a2eef1-1cbf-4855-b78f-b54f52b51a71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371230534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2371230534
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3553806621
Short name T173
Test name
Test status
Simulation time 240066391323 ps
CPU time 91.13 seconds
Started Jul 18 04:42:34 PM PDT 24
Finished Jul 18 04:44:06 PM PDT 24
Peak memory 194112 kb
Host smart-974a19cb-55dc-4710-bcaf-d6f251af0920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553806621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3553806621
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.3276259556
Short name T144
Test name
Test status
Simulation time 392548525397 ps
CPU time 452.26 seconds
Started Jul 18 04:43:37 PM PDT 24
Finished Jul 18 04:51:12 PM PDT 24
Peak memory 191524 kb
Host smart-5d59a089-633d-48fa-adc8-d5a7893e3127
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276259556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3276259556
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random.3624047361
Short name T298
Test name
Test status
Simulation time 472159104101 ps
CPU time 294.03 seconds
Started Jul 18 04:43:08 PM PDT 24
Finished Jul 18 04:48:03 PM PDT 24
Peak memory 191556 kb
Host smart-d6f9684b-e352-4d0b-85d5-53f4ab69f6b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624047361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3624047361
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1685131701
Short name T275
Test name
Test status
Simulation time 2194999229694 ps
CPU time 1106.21 seconds
Started Jul 18 04:43:09 PM PDT 24
Finished Jul 18 05:01:36 PM PDT 24
Peak memory 183340 kb
Host smart-43b9cb47-83b9-4d86-a3bc-e9a18a9699e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685131701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1685131701
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/59.rv_timer_random.2479506619
Short name T312
Test name
Test status
Simulation time 56850495327 ps
CPU time 272.45 seconds
Started Jul 18 04:43:31 PM PDT 24
Finished Jul 18 04:48:06 PM PDT 24
Peak memory 195220 kb
Host smart-45715330-4dd6-428b-8f78-d2da2310d560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479506619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2479506619
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1692052354
Short name T89
Test name
Test status
Simulation time 21839254 ps
CPU time 0.65 seconds
Started Jul 18 04:41:38 PM PDT 24
Finished Jul 18 04:41:40 PM PDT 24
Peak memory 182360 kb
Host smart-c8ad3cca-033a-4b1c-91fb-798ddd8cfc00
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692052354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1692052354
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1019865667
Short name T354
Test name
Test status
Simulation time 956769085126 ps
CPU time 921.4 seconds
Started Jul 18 04:42:37 PM PDT 24
Finished Jul 18 04:58:01 PM PDT 24
Peak memory 183460 kb
Host smart-f34be165-3f07-4cef-acc2-1d04e7f960db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019865667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1019865667
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/119.rv_timer_random.3988415945
Short name T21
Test name
Test status
Simulation time 2520375909493 ps
CPU time 625.15 seconds
Started Jul 18 04:43:37 PM PDT 24
Finished Jul 18 04:54:05 PM PDT 24
Peak memory 191592 kb
Host smart-ed30b534-cd90-47c3-a4e6-cac823ee2627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988415945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3988415945
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.4193728324
Short name T194
Test name
Test status
Simulation time 145601360524 ps
CPU time 140.3 seconds
Started Jul 18 04:43:23 PM PDT 24
Finished Jul 18 04:45:46 PM PDT 24
Peak memory 191568 kb
Host smart-2309e0ef-402f-445a-afce-6a4de0fd54f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193728324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.4193728324
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2311300256
Short name T244
Test name
Test status
Simulation time 281750520669 ps
CPU time 211.57 seconds
Started Jul 18 04:43:42 PM PDT 24
Finished Jul 18 04:47:15 PM PDT 24
Peak memory 191552 kb
Host smart-0eca873e-2950-4da2-aead-111e973b4f13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311300256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2311300256
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.3287547904
Short name T304
Test name
Test status
Simulation time 65474014478 ps
CPU time 98.27 seconds
Started Jul 18 04:42:44 PM PDT 24
Finished Jul 18 04:44:24 PM PDT 24
Peak memory 191556 kb
Host smart-7438cc71-3e23-4eee-8def-f6ad0f3fadbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287547904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3287547904
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3599497598
Short name T68
Test name
Test status
Simulation time 967402988399 ps
CPU time 989.89 seconds
Started Jul 18 04:42:41 PM PDT 24
Finished Jul 18 04:59:14 PM PDT 24
Peak memory 191564 kb
Host smart-d82956aa-3764-4dbe-a819-25aaa6eb9085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599497598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3599497598
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_random.414595183
Short name T307
Test name
Test status
Simulation time 242594434196 ps
CPU time 188.76 seconds
Started Jul 18 04:42:40 PM PDT 24
Finished Jul 18 04:45:52 PM PDT 24
Peak memory 191976 kb
Host smart-90562ee4-78e9-4890-85c8-c8f786662dcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414595183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.414595183
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.4238543236
Short name T164
Test name
Test status
Simulation time 131336419698 ps
CPU time 200.32 seconds
Started Jul 18 04:43:38 PM PDT 24
Finished Jul 18 04:47:00 PM PDT 24
Peak memory 191592 kb
Host smart-275747ba-49ef-40d1-9329-57118a9ca444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238543236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.4238543236
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.988708217
Short name T214
Test name
Test status
Simulation time 242909771867 ps
CPU time 286.06 seconds
Started Jul 18 04:43:45 PM PDT 24
Finished Jul 18 04:48:33 PM PDT 24
Peak memory 191552 kb
Host smart-bb5b333c-68d9-4e4e-99d5-be7697d65fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988708217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.988708217
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random.4257869418
Short name T242
Test name
Test status
Simulation time 192412942152 ps
CPU time 448.5 seconds
Started Jul 18 04:42:58 PM PDT 24
Finished Jul 18 04:50:28 PM PDT 24
Peak memory 191552 kb
Host smart-1b790dfe-b9ee-43cb-bdf3-172ed7a16cf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257869418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.4257869418
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.103211710
Short name T310
Test name
Test status
Simulation time 21534729460 ps
CPU time 10.19 seconds
Started Jul 18 04:43:11 PM PDT 24
Finished Jul 18 04:43:24 PM PDT 24
Peak memory 183352 kb
Host smart-bd6c10c0-cad8-4bac-98d2-62cad385803b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103211710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.103211710
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2501206615
Short name T279
Test name
Test status
Simulation time 2179529971294 ps
CPU time 1588.63 seconds
Started Jul 18 04:43:24 PM PDT 24
Finished Jul 18 05:09:56 PM PDT 24
Peak memory 191572 kb
Host smart-0e71a197-bf7b-40e7-b0e7-85c2c8385155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501206615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2501206615
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.2512771872
Short name T179
Test name
Test status
Simulation time 137542795580 ps
CPU time 684.9 seconds
Started Jul 18 04:43:19 PM PDT 24
Finished Jul 18 04:54:45 PM PDT 24
Peak memory 191564 kb
Host smart-6b308d5a-081f-4a57-9aaf-95e59b90699d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512771872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2512771872
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.609270095
Short name T190
Test name
Test status
Simulation time 658622992456 ps
CPU time 430.51 seconds
Started Jul 18 04:43:28 PM PDT 24
Finished Jul 18 04:50:42 PM PDT 24
Peak memory 191540 kb
Host smart-dbfe1b66-6a9a-4b6a-b08a-1dd737070371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609270095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.609270095
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4134538911
Short name T108
Test name
Test status
Simulation time 135397474 ps
CPU time 1.23 seconds
Started Jul 18 04:41:57 PM PDT 24
Finished Jul 18 04:42:03 PM PDT 24
Peak memory 194644 kb
Host smart-8d3f8134-07bb-4a23-bf90-efbeb43e82f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134538911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.4134538911
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.4229226181
Short name T219
Test name
Test status
Simulation time 90497684433 ps
CPU time 88.16 seconds
Started Jul 18 04:42:24 PM PDT 24
Finished Jul 18 04:43:53 PM PDT 24
Peak memory 191548 kb
Host smart-193b983f-51ed-42e4-8938-131520e7c2e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229226181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
4229226181
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3536909573
Short name T188
Test name
Test status
Simulation time 1226914483115 ps
CPU time 678.62 seconds
Started Jul 18 04:42:33 PM PDT 24
Finished Jul 18 04:53:52 PM PDT 24
Peak memory 183352 kb
Host smart-7e04b9b8-6513-46fb-b7cb-ba2813655c41
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536909573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3536909573
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/102.rv_timer_random.3225202743
Short name T152
Test name
Test status
Simulation time 99630270344 ps
CPU time 156.63 seconds
Started Jul 18 04:43:29 PM PDT 24
Finished Jul 18 04:46:09 PM PDT 24
Peak memory 191604 kb
Host smart-ca268f7c-7766-4ce1-862d-8b2613f06cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225202743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3225202743
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.317915969
Short name T322
Test name
Test status
Simulation time 175534323880 ps
CPU time 156.28 seconds
Started Jul 18 04:43:39 PM PDT 24
Finished Jul 18 04:46:17 PM PDT 24
Peak memory 191296 kb
Host smart-bf0b5cc9-dca5-467d-87d4-955fdf79ab92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317915969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.317915969
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.910685935
Short name T75
Test name
Test status
Simulation time 263959146559 ps
CPU time 254.46 seconds
Started Jul 18 04:42:35 PM PDT 24
Finished Jul 18 04:46:51 PM PDT 24
Peak memory 193916 kb
Host smart-a5dd0685-a765-42e9-9936-e5d547641aff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910685935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.910685935
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.832648457
Short name T324
Test name
Test status
Simulation time 237683874117 ps
CPU time 109.22 seconds
Started Jul 18 04:43:23 PM PDT 24
Finished Jul 18 04:45:15 PM PDT 24
Peak memory 191596 kb
Host smart-8f491668-f200-4fde-a64f-a8d0f8e56a3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832648457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.832648457
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3140961376
Short name T256
Test name
Test status
Simulation time 54246854325 ps
CPU time 206.13 seconds
Started Jul 18 04:43:29 PM PDT 24
Finished Jul 18 04:46:58 PM PDT 24
Peak memory 183344 kb
Host smart-5254dc51-4abf-4933-895b-30f3e1d45c9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140961376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3140961376
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2549313478
Short name T161
Test name
Test status
Simulation time 256335615802 ps
CPU time 208.87 seconds
Started Jul 18 04:43:35 PM PDT 24
Finished Jul 18 04:47:07 PM PDT 24
Peak memory 191600 kb
Host smart-d83e7d21-96ee-43fc-b6a7-8666435cca86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549313478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2549313478
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.4065881361
Short name T349
Test name
Test status
Simulation time 621010242509 ps
CPU time 1349.82 seconds
Started Jul 18 04:43:35 PM PDT 24
Finished Jul 18 05:06:08 PM PDT 24
Peak memory 191596 kb
Host smart-259e21f5-25ee-4044-b835-20c1c806dad2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065881361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.4065881361
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.294337420
Short name T287
Test name
Test status
Simulation time 352314137739 ps
CPU time 217.59 seconds
Started Jul 18 04:43:32 PM PDT 24
Finished Jul 18 04:47:13 PM PDT 24
Peak memory 191296 kb
Host smart-8bda3620-08c1-4ff7-a52e-ef910e1c37b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294337420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.294337420
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.3751671764
Short name T206
Test name
Test status
Simulation time 70977479562 ps
CPU time 102.25 seconds
Started Jul 18 04:43:24 PM PDT 24
Finished Jul 18 04:45:09 PM PDT 24
Peak memory 191548 kb
Host smart-0ea151b4-0e6a-4bed-99f3-56b284bf69ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751671764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3751671764
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.44194732
Short name T327
Test name
Test status
Simulation time 527071662563 ps
CPU time 633.43 seconds
Started Jul 18 04:43:32 PM PDT 24
Finished Jul 18 04:54:09 PM PDT 24
Peak memory 191420 kb
Host smart-7974c612-7bbb-40fe-aba4-e9dac488a857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44194732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.44194732
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3454526308
Short name T227
Test name
Test status
Simulation time 69522000429 ps
CPU time 178.42 seconds
Started Jul 18 04:43:42 PM PDT 24
Finished Jul 18 04:46:42 PM PDT 24
Peak memory 191596 kb
Host smart-a024b341-e7e0-4a5d-aba8-db4edcae8892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454526308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3454526308
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.4150861017
Short name T247
Test name
Test status
Simulation time 42708610859 ps
CPU time 286.7 seconds
Started Jul 18 04:43:37 PM PDT 24
Finished Jul 18 04:48:26 PM PDT 24
Peak memory 194128 kb
Host smart-fe865329-730c-4525-85d9-cb671e631639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150861017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.4150861017
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.877306196
Short name T2
Test name
Test status
Simulation time 162756393508 ps
CPU time 139.44 seconds
Started Jul 18 04:44:45 PM PDT 24
Finished Jul 18 04:47:05 PM PDT 24
Peak memory 191288 kb
Host smart-87a410b3-ba33-4d66-b500-655a082c2510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877306196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.877306196
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3047622244
Short name T248
Test name
Test status
Simulation time 216156797069 ps
CPU time 102.6 seconds
Started Jul 18 04:42:45 PM PDT 24
Finished Jul 18 04:44:30 PM PDT 24
Peak memory 183460 kb
Host smart-cae98fe0-6dfc-498d-a953-ccdfc3f18085
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047622244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3047622244
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_random.2738541978
Short name T131
Test name
Test status
Simulation time 545821329041 ps
CPU time 415.94 seconds
Started Jul 18 04:42:59 PM PDT 24
Finished Jul 18 04:49:56 PM PDT 24
Peak memory 191548 kb
Host smart-bf1b1316-a240-4c77-be62-1e5debaebb98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738541978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2738541978
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.371823777
Short name T213
Test name
Test status
Simulation time 839005151274 ps
CPU time 451.22 seconds
Started Jul 18 04:42:47 PM PDT 24
Finished Jul 18 04:50:22 PM PDT 24
Peak memory 183340 kb
Host smart-65a73fd3-cef0-4854-bbc2-1da99711017c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371823777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.371823777
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2241376338
Short name T348
Test name
Test status
Simulation time 1046688977816 ps
CPU time 904.24 seconds
Started Jul 18 04:42:51 PM PDT 24
Finished Jul 18 04:57:58 PM PDT 24
Peak memory 191556 kb
Host smart-32c86222-0c92-458c-b302-1a6b7851d556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241376338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2241376338
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_random.3362857269
Short name T270
Test name
Test status
Simulation time 349536320665 ps
CPU time 370.44 seconds
Started Jul 18 04:43:03 PM PDT 24
Finished Jul 18 04:49:15 PM PDT 24
Peak memory 191564 kb
Host smart-ed8e5cfa-5868-4640-8415-a0dd00a39f42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362857269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3362857269
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3473436379
Short name T98
Test name
Test status
Simulation time 129043063274 ps
CPU time 93.99 seconds
Started Jul 18 04:43:02 PM PDT 24
Finished Jul 18 04:44:38 PM PDT 24
Peak memory 191544 kb
Host smart-e8f242fd-c066-4c80-81d3-d4b1a8de9cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473436379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3473436379
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_random.1109531477
Short name T178
Test name
Test status
Simulation time 933141004727 ps
CPU time 465.54 seconds
Started Jul 18 04:43:04 PM PDT 24
Finished Jul 18 04:50:52 PM PDT 24
Peak memory 191556 kb
Host smart-bbef608a-d662-44d3-9366-e54f7e5b9d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109531477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1109531477
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random.3319075958
Short name T268
Test name
Test status
Simulation time 62277665081 ps
CPU time 1443.88 seconds
Started Jul 18 04:42:24 PM PDT 24
Finished Jul 18 05:06:29 PM PDT 24
Peak memory 191564 kb
Host smart-3d7ae2b4-003b-4470-8797-d5e1723b3b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319075958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3319075958
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1557572318
Short name T325
Test name
Test status
Simulation time 416219896261 ps
CPU time 227.16 seconds
Started Jul 18 04:43:15 PM PDT 24
Finished Jul 18 04:47:03 PM PDT 24
Peak memory 183340 kb
Host smart-87c9ae4e-d920-47f4-a4fb-2beba836ba9c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557572318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1557572318
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/57.rv_timer_random.203728797
Short name T71
Test name
Test status
Simulation time 451883319361 ps
CPU time 383.82 seconds
Started Jul 18 04:43:25 PM PDT 24
Finished Jul 18 04:49:52 PM PDT 24
Peak memory 191676 kb
Host smart-c2347316-63bb-487f-8535-73bdbc1db31c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203728797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.203728797
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.187784957
Short name T120
Test name
Test status
Simulation time 524430833492 ps
CPU time 583.95 seconds
Started Jul 18 04:43:18 PM PDT 24
Finished Jul 18 04:53:04 PM PDT 24
Peak memory 191544 kb
Host smart-903d706e-809b-4060-91c7-8d50515b1b08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187784957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.187784957
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3300484155
Short name T252
Test name
Test status
Simulation time 291202395292 ps
CPU time 150.19 seconds
Started Jul 18 04:43:15 PM PDT 24
Finished Jul 18 04:45:47 PM PDT 24
Peak memory 191664 kb
Host smart-13f6af2e-69c8-4c70-b272-137b435b3929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300484155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3300484155
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.4026365687
Short name T331
Test name
Test status
Simulation time 853414697109 ps
CPU time 647.94 seconds
Started Jul 18 04:42:23 PM PDT 24
Finished Jul 18 04:53:13 PM PDT 24
Peak memory 191544 kb
Host smart-5491cf41-93fc-4015-940d-98a8ae29b6ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026365687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
4026365687
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4206375264
Short name T81
Test name
Test status
Simulation time 205692298 ps
CPU time 0.78 seconds
Started Jul 18 04:41:40 PM PDT 24
Finished Jul 18 04:41:43 PM PDT 24
Peak memory 192228 kb
Host smart-d8d0a9f4-ac11-406e-a766-cb1d9a266bcd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206375264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.4206375264
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.637772270
Short name T106
Test name
Test status
Simulation time 197155989 ps
CPU time 2.83 seconds
Started Jul 18 04:41:39 PM PDT 24
Finished Jul 18 04:41:43 PM PDT 24
Peak memory 190624 kb
Host smart-0794aab7-adf4-4291-8ecf-49a3ed8500fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637772270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.637772270
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.189622064
Short name T491
Test name
Test status
Simulation time 24469921 ps
CPU time 0.54 seconds
Started Jul 18 04:41:49 PM PDT 24
Finished Jul 18 04:41:51 PM PDT 24
Peak memory 182360 kb
Host smart-fe4c68fd-7e26-44c8-9d2d-75cd59bf81b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189622064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.189622064
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3042530782
Short name T480
Test name
Test status
Simulation time 72748987 ps
CPU time 1.03 seconds
Started Jul 18 04:41:40 PM PDT 24
Finished Jul 18 04:41:43 PM PDT 24
Peak memory 197000 kb
Host smart-8baea14a-cb1d-4f16-8fa4-cfb945219508
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042530782 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3042530782
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1606425795
Short name T535
Test name
Test status
Simulation time 19034853 ps
CPU time 0.59 seconds
Started Jul 18 04:41:43 PM PDT 24
Finished Jul 18 04:41:45 PM PDT 24
Peak memory 182216 kb
Host smart-c67c268f-7b07-4336-b645-62d9a3722988
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606425795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1606425795
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.425796441
Short name T475
Test name
Test status
Simulation time 32535093 ps
CPU time 0.55 seconds
Started Jul 18 04:41:38 PM PDT 24
Finished Jul 18 04:41:40 PM PDT 24
Peak memory 182344 kb
Host smart-f52233a4-9e9c-49be-8490-77257eee785c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425796441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.425796441
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1596041521
Short name T567
Test name
Test status
Simulation time 34913226 ps
CPU time 0.78 seconds
Started Jul 18 04:50:27 PM PDT 24
Finished Jul 18 04:50:28 PM PDT 24
Peak memory 190652 kb
Host smart-66fbc557-2b8b-4eac-93b8-311c0aa5849e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596041521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1596041521
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3366885746
Short name T483
Test name
Test status
Simulation time 145937201 ps
CPU time 2.1 seconds
Started Jul 18 04:41:50 PM PDT 24
Finished Jul 18 04:41:53 PM PDT 24
Peak memory 197080 kb
Host smart-4f92cfa6-cb10-47a2-8349-6d2bbd71e947
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366885746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3366885746
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3966803480
Short name T570
Test name
Test status
Simulation time 147441234 ps
CPU time 0.98 seconds
Started Jul 18 04:41:41 PM PDT 24
Finished Jul 18 04:41:44 PM PDT 24
Peak memory 193408 kb
Host smart-27124bb7-896c-427b-8904-b8c15baad932
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966803480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3966803480
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.4293287325
Short name T84
Test name
Test status
Simulation time 65959190 ps
CPU time 0.64 seconds
Started Jul 18 04:41:50 PM PDT 24
Finished Jul 18 04:41:53 PM PDT 24
Peak memory 182344 kb
Host smart-88bc9061-f926-4525-ad86-c8221ccfd6c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293287325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.4293287325
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3194692185
Short name T490
Test name
Test status
Simulation time 39572326 ps
CPU time 1.46 seconds
Started Jul 18 04:41:48 PM PDT 24
Finished Jul 18 04:41:51 PM PDT 24
Peak memory 191684 kb
Host smart-adf32ead-25fb-4490-a869-462cc47e7996
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194692185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3194692185
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1870503989
Short name T92
Test name
Test status
Simulation time 41081224 ps
CPU time 0.56 seconds
Started Jul 18 04:41:44 PM PDT 24
Finished Jul 18 04:41:46 PM PDT 24
Peak memory 182372 kb
Host smart-122951ef-c906-4a59-9a11-84f657df3c60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870503989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1870503989
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1727459481
Short name T519
Test name
Test status
Simulation time 19985767 ps
CPU time 0.63 seconds
Started Jul 18 04:41:48 PM PDT 24
Finished Jul 18 04:41:50 PM PDT 24
Peak memory 193484 kb
Host smart-99aae04a-396b-46a6-802a-8b51609d5b73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727459481 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1727459481
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.48977254
Short name T556
Test name
Test status
Simulation time 25308454 ps
CPU time 0.57 seconds
Started Jul 18 04:41:41 PM PDT 24
Finished Jul 18 04:41:44 PM PDT 24
Peak memory 182348 kb
Host smart-d3ab5cea-a294-435d-ac5a-34eef9c9a523
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48977254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.48977254
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3975205348
Short name T479
Test name
Test status
Simulation time 52070579 ps
CPU time 0.61 seconds
Started Jul 18 04:41:41 PM PDT 24
Finished Jul 18 04:41:43 PM PDT 24
Peak memory 182640 kb
Host smart-137ad4b8-8781-4ba2-94c8-157046aeaf0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975205348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3975205348
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3381330267
Short name T521
Test name
Test status
Simulation time 248198568 ps
CPU time 0.83 seconds
Started Jul 18 04:41:37 PM PDT 24
Finished Jul 18 04:41:39 PM PDT 24
Peak memory 191288 kb
Host smart-dfc1fecd-758b-4121-ae4c-1773aafc1529
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381330267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3381330267
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2187684906
Short name T497
Test name
Test status
Simulation time 329802014 ps
CPU time 3.13 seconds
Started Jul 18 04:41:38 PM PDT 24
Finished Jul 18 04:41:42 PM PDT 24
Peak memory 197068 kb
Host smart-e6f8e56d-16f8-41e2-a5dd-b16f81d39d65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187684906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2187684906
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1566501599
Short name T474
Test name
Test status
Simulation time 113585181 ps
CPU time 0.9 seconds
Started Jul 18 04:41:33 PM PDT 24
Finished Jul 18 04:41:35 PM PDT 24
Peak memory 193212 kb
Host smart-2cb22fa0-8ee3-400c-af3f-1f7d059cab04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566501599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1566501599
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1656118732
Short name T484
Test name
Test status
Simulation time 21860296 ps
CPU time 0.68 seconds
Started Jul 18 04:42:00 PM PDT 24
Finished Jul 18 04:42:05 PM PDT 24
Peak memory 194000 kb
Host smart-1e0bbdf5-636d-4b7a-b50c-09c5e0aa5045
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656118732 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1656118732
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1122995165
Short name T576
Test name
Test status
Simulation time 32453635 ps
CPU time 0.55 seconds
Started Jul 18 04:41:52 PM PDT 24
Finished Jul 18 04:41:55 PM PDT 24
Peak memory 181208 kb
Host smart-84150b73-67cd-4c63-8277-1c2f0d75c3d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122995165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1122995165
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1272117944
Short name T579
Test name
Test status
Simulation time 35579125 ps
CPU time 0.53 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:02 PM PDT 24
Peak memory 181944 kb
Host smart-bb9ab794-5ec6-48d6-a8a8-fc15c879ee52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272117944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1272117944
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1184583912
Short name T49
Test name
Test status
Simulation time 124566747 ps
CPU time 0.76 seconds
Started Jul 18 04:41:54 PM PDT 24
Finished Jul 18 04:41:57 PM PDT 24
Peak memory 192992 kb
Host smart-4486648a-ed0d-4b9e-91e9-6a530699927d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184583912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1184583912
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1912242285
Short name T533
Test name
Test status
Simulation time 164250193 ps
CPU time 1.96 seconds
Started Jul 18 04:41:58 PM PDT 24
Finished Jul 18 04:42:05 PM PDT 24
Peak memory 197456 kb
Host smart-e73c8cfc-ce2d-483e-a91b-2810659f3d47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912242285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1912242285
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1861360508
Short name T566
Test name
Test status
Simulation time 46578195 ps
CPU time 0.83 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:01 PM PDT 24
Peak memory 193444 kb
Host smart-f7aca438-e1de-4041-98a8-e23ca843e144
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861360508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1861360508
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1453070058
Short name T520
Test name
Test status
Simulation time 33012761 ps
CPU time 1.39 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:02 PM PDT 24
Peak memory 197096 kb
Host smart-2027fb03-bf04-47b2-9859-072ed450ba39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453070058 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1453070058
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3012473166
Short name T493
Test name
Test status
Simulation time 50205929 ps
CPU time 0.58 seconds
Started Jul 18 04:42:05 PM PDT 24
Finished Jul 18 04:42:10 PM PDT 24
Peak memory 182368 kb
Host smart-2e97975c-f07c-4335-bad6-92289df19a22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012473166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3012473166
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.120979025
Short name T529
Test name
Test status
Simulation time 54555720 ps
CPU time 0.56 seconds
Started Jul 18 04:42:01 PM PDT 24
Finished Jul 18 04:42:05 PM PDT 24
Peak memory 182236 kb
Host smart-da079d93-0063-419c-8ec9-1b7fa079c0cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120979025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.120979025
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1994315672
Short name T575
Test name
Test status
Simulation time 106626083 ps
CPU time 0.59 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:01 PM PDT 24
Peak memory 191040 kb
Host smart-65a07f94-9c88-4522-947d-ff3792daf238
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994315672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1994315672
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1684008902
Short name T50
Test name
Test status
Simulation time 1084097135 ps
CPU time 3.76 seconds
Started Jul 18 04:42:07 PM PDT 24
Finished Jul 18 04:42:14 PM PDT 24
Peak memory 197068 kb
Host smart-6410eb9e-4d8e-496f-814f-f2773dc98d8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684008902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1684008902
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.994988481
Short name T509
Test name
Test status
Simulation time 89107506 ps
CPU time 1.12 seconds
Started Jul 18 04:42:13 PM PDT 24
Finished Jul 18 04:42:17 PM PDT 24
Peak memory 195908 kb
Host smart-42e2e246-81e5-4ca4-81c6-d4c478a7b1ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994988481 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.994988481
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.996135676
Short name T578
Test name
Test status
Simulation time 49133779 ps
CPU time 0.56 seconds
Started Jul 18 04:41:57 PM PDT 24
Finished Jul 18 04:42:02 PM PDT 24
Peak memory 182388 kb
Host smart-b6a9031f-f4d5-452a-9388-f88d5d0d875c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996135676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.996135676
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1776312794
Short name T498
Test name
Test status
Simulation time 31754095 ps
CPU time 0.6 seconds
Started Jul 18 04:41:57 PM PDT 24
Finished Jul 18 04:42:02 PM PDT 24
Peak memory 182244 kb
Host smart-5ed8ab15-e39a-4e11-a034-5ffd0e1b36ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776312794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1776312794
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3900062086
Short name T531
Test name
Test status
Simulation time 118132920 ps
CPU time 0.76 seconds
Started Jul 18 04:42:02 PM PDT 24
Finished Jul 18 04:42:07 PM PDT 24
Peak memory 191312 kb
Host smart-f51c544e-685e-4e57-9418-b14b4bc13d84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900062086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3900062086
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.644960343
Short name T536
Test name
Test status
Simulation time 499138137 ps
CPU time 2.58 seconds
Started Jul 18 04:42:00 PM PDT 24
Finished Jul 18 04:42:07 PM PDT 24
Peak memory 197128 kb
Host smart-4719dc51-402f-4cd1-99c0-cbcb65c259ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644960343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.644960343
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2457718279
Short name T513
Test name
Test status
Simulation time 67813819 ps
CPU time 0.91 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:01 PM PDT 24
Peak memory 196412 kb
Host smart-d1693a38-06cf-44d9-b4d0-01b8d4ebaf78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457718279 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2457718279
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3811285906
Short name T32
Test name
Test status
Simulation time 39303727 ps
CPU time 0.55 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:00 PM PDT 24
Peak memory 182360 kb
Host smart-0d4cf0c5-fcc4-4c8a-a472-924a02e0c7fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811285906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3811285906
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2590902348
Short name T468
Test name
Test status
Simulation time 56877095 ps
CPU time 0.56 seconds
Started Jul 18 04:42:07 PM PDT 24
Finished Jul 18 04:42:11 PM PDT 24
Peak memory 182256 kb
Host smart-a7b9bd5e-ecc4-42ee-b6bb-95c5493a508a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590902348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2590902348
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3223495261
Short name T499
Test name
Test status
Simulation time 113558003 ps
CPU time 0.61 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:01 PM PDT 24
Peak memory 191068 kb
Host smart-7b6c08d0-5c8d-4604-9b46-bc80b4b41722
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223495261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3223495261
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.849483643
Short name T551
Test name
Test status
Simulation time 56566812 ps
CPU time 1.24 seconds
Started Jul 18 04:42:01 PM PDT 24
Finished Jul 18 04:42:06 PM PDT 24
Peak memory 197020 kb
Host smart-3db730d2-b85a-4d16-89f0-719f4041e237
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849483643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.849483643
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.328987920
Short name T511
Test name
Test status
Simulation time 38652612 ps
CPU time 0.79 seconds
Started Jul 18 04:42:08 PM PDT 24
Finished Jul 18 04:42:12 PM PDT 24
Peak memory 193096 kb
Host smart-4aec6548-8ea0-4e51-9b0c-0750492487f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328987920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.328987920
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2281899370
Short name T564
Test name
Test status
Simulation time 36270000 ps
CPU time 0.92 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:01 PM PDT 24
Peak memory 196944 kb
Host smart-c59eac75-1d4d-488a-8a0d-1d62edd8a203
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281899370 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2281899370
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3796270369
Short name T554
Test name
Test status
Simulation time 43734083 ps
CPU time 0.61 seconds
Started Jul 18 04:41:51 PM PDT 24
Finished Jul 18 04:41:53 PM PDT 24
Peak memory 182372 kb
Host smart-caef20e5-f6f9-4b84-883a-2db9cc601d8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796270369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3796270369
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2757863540
Short name T469
Test name
Test status
Simulation time 11702272 ps
CPU time 0.55 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:01 PM PDT 24
Peak memory 182212 kb
Host smart-c174a4c0-8d19-4a4a-bac3-cd1338864fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757863540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2757863540
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3237907844
Short name T69
Test name
Test status
Simulation time 54616630 ps
CPU time 0.66 seconds
Started Jul 18 04:41:55 PM PDT 24
Finished Jul 18 04:42:00 PM PDT 24
Peak memory 191656 kb
Host smart-acd2d5f9-f937-43cd-87d4-a437dff815fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237907844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3237907844
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3835502904
Short name T495
Test name
Test status
Simulation time 136604517 ps
CPU time 1.29 seconds
Started Jul 18 04:41:55 PM PDT 24
Finished Jul 18 04:42:00 PM PDT 24
Peak memory 197068 kb
Host smart-aae3be7b-457f-44de-95db-fd305611005b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835502904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3835502904
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1543203242
Short name T569
Test name
Test status
Simulation time 474682388 ps
CPU time 1.34 seconds
Started Jul 18 04:42:05 PM PDT 24
Finished Jul 18 04:42:11 PM PDT 24
Peak memory 194992 kb
Host smart-51962a44-15b4-410b-9e8c-fc2cdc0de54f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543203242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1543203242
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3058499235
Short name T488
Test name
Test status
Simulation time 32734380 ps
CPU time 0.92 seconds
Started Jul 18 04:41:58 PM PDT 24
Finished Jul 18 04:42:03 PM PDT 24
Peak memory 196124 kb
Host smart-365e71ce-684b-428b-877a-f6e02d03d2cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058499235 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3058499235
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2291835313
Short name T485
Test name
Test status
Simulation time 15472466 ps
CPU time 0.58 seconds
Started Jul 18 04:41:55 PM PDT 24
Finished Jul 18 04:42:00 PM PDT 24
Peak memory 182392 kb
Host smart-a831d760-44ae-44aa-9390-2b9819993c0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291835313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2291835313
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.406459179
Short name T501
Test name
Test status
Simulation time 21286460 ps
CPU time 0.54 seconds
Started Jul 18 04:42:03 PM PDT 24
Finished Jul 18 04:42:08 PM PDT 24
Peak memory 181708 kb
Host smart-8385cf9e-7c47-41d5-b186-48645ad494ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406459179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.406459179
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2072323832
Short name T79
Test name
Test status
Simulation time 62163371 ps
CPU time 0.73 seconds
Started Jul 18 04:42:05 PM PDT 24
Finished Jul 18 04:42:09 PM PDT 24
Peak memory 192812 kb
Host smart-74d9b232-4b4c-434f-a2b2-97dd0bebbf08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072323832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2072323832
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3769467608
Short name T45
Test name
Test status
Simulation time 1062339940 ps
CPU time 1.51 seconds
Started Jul 18 04:42:05 PM PDT 24
Finished Jul 18 04:42:11 PM PDT 24
Peak memory 197064 kb
Host smart-1f68fada-2f1f-45df-a03f-4dafcf7df201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769467608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3769467608
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3484811620
Short name T110
Test name
Test status
Simulation time 494433916 ps
CPU time 1.34 seconds
Started Jul 18 04:41:51 PM PDT 24
Finished Jul 18 04:41:53 PM PDT 24
Peak memory 182700 kb
Host smart-8bade233-813b-43b5-9bb2-26aa1ad9d37a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484811620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3484811620
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2185931781
Short name T487
Test name
Test status
Simulation time 65444717 ps
CPU time 0.83 seconds
Started Jul 18 04:41:51 PM PDT 24
Finished Jul 18 04:41:54 PM PDT 24
Peak memory 196924 kb
Host smart-299b9b95-2b55-4948-8fe0-c0fff3f00934
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185931781 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2185931781
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.456143450
Short name T539
Test name
Test status
Simulation time 18286290 ps
CPU time 0.54 seconds
Started Jul 18 04:41:52 PM PDT 24
Finished Jul 18 04:41:55 PM PDT 24
Peak memory 182344 kb
Host smart-7d3d8509-7893-4246-b215-ee8aad69d316
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456143450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.456143450
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1258338099
Short name T518
Test name
Test status
Simulation time 17883476 ps
CPU time 0.55 seconds
Started Jul 18 04:41:52 PM PDT 24
Finished Jul 18 04:41:56 PM PDT 24
Peak memory 182220 kb
Host smart-f948ff90-283f-438e-8756-6fadc05abab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258338099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1258338099
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2118208366
Short name T548
Test name
Test status
Simulation time 58952483 ps
CPU time 0.8 seconds
Started Jul 18 04:41:58 PM PDT 24
Finished Jul 18 04:42:03 PM PDT 24
Peak memory 191284 kb
Host smart-1040afa8-a24f-4411-b0dd-6c57f8e5cf41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118208366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2118208366
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.28803448
Short name T464
Test name
Test status
Simulation time 58190184 ps
CPU time 1.16 seconds
Started Jul 18 04:42:05 PM PDT 24
Finished Jul 18 04:42:10 PM PDT 24
Peak memory 195760 kb
Host smart-40b836ca-c116-497e-a699-f2024aee2847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28803448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.28803448
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.4166824958
Short name T481
Test name
Test status
Simulation time 172499478 ps
CPU time 0.88 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:01 PM PDT 24
Peak memory 193484 kb
Host smart-8e2914a5-6edd-49dc-a3fc-7381afd74444
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166824958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.4166824958
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1872051513
Short name T459
Test name
Test status
Simulation time 77716254 ps
CPU time 1.2 seconds
Started Jul 18 04:42:09 PM PDT 24
Finished Jul 18 04:42:13 PM PDT 24
Peak memory 196968 kb
Host smart-e047014a-4d57-4862-bd74-f6206631ce72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872051513 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1872051513
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1409676489
Short name T525
Test name
Test status
Simulation time 20395327 ps
CPU time 0.56 seconds
Started Jul 18 04:42:07 PM PDT 24
Finished Jul 18 04:42:11 PM PDT 24
Peak memory 181708 kb
Host smart-a600d622-0d43-4c92-95f3-f4a66e1cb550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409676489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1409676489
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.266163997
Short name T96
Test name
Test status
Simulation time 134517331 ps
CPU time 0.77 seconds
Started Jul 18 04:42:19 PM PDT 24
Finished Jul 18 04:42:23 PM PDT 24
Peak memory 192976 kb
Host smart-564804ac-2193-4af8-9d3f-09420014cf57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266163997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.266163997
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.918305777
Short name T505
Test name
Test status
Simulation time 94392251 ps
CPU time 2.02 seconds
Started Jul 18 04:41:55 PM PDT 24
Finished Jul 18 04:42:02 PM PDT 24
Peak memory 197120 kb
Host smart-e6acc054-bf38-4b87-abbd-6290c692c721
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918305777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.918305777
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2633783399
Short name T546
Test name
Test status
Simulation time 192768933 ps
CPU time 1.1 seconds
Started Jul 18 04:42:06 PM PDT 24
Finished Jul 18 04:42:11 PM PDT 24
Peak memory 182748 kb
Host smart-d09746a7-eeff-4c44-bf2c-55e02fe7f3c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633783399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2633783399
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1670341791
Short name T530
Test name
Test status
Simulation time 33594915 ps
CPU time 0.9 seconds
Started Jul 18 04:42:05 PM PDT 24
Finished Jul 18 04:42:10 PM PDT 24
Peak memory 196336 kb
Host smart-d0ff2c9d-5b9f-4352-97e2-d3d57dddcbad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670341791 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1670341791
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2542159013
Short name T504
Test name
Test status
Simulation time 38837384 ps
CPU time 0.55 seconds
Started Jul 18 04:42:03 PM PDT 24
Finished Jul 18 04:42:06 PM PDT 24
Peak memory 182348 kb
Host smart-41e7de8c-b31a-41c7-8316-3ce0b3228ec1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542159013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2542159013
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3274839835
Short name T573
Test name
Test status
Simulation time 91203063 ps
CPU time 0.55 seconds
Started Jul 18 04:42:16 PM PDT 24
Finished Jul 18 04:42:19 PM PDT 24
Peak memory 182224 kb
Host smart-fbb0d258-d3f2-45e7-bfdc-68d19508a82a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274839835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3274839835
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3566535350
Short name T80
Test name
Test status
Simulation time 50472645 ps
CPU time 0.62 seconds
Started Jul 18 04:42:05 PM PDT 24
Finished Jul 18 04:42:10 PM PDT 24
Peak memory 191756 kb
Host smart-d1c3a87c-1525-4b95-9b6e-20bbef39d559
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566535350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3566535350
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.660870715
Short name T486
Test name
Test status
Simulation time 77382549 ps
CPU time 1.07 seconds
Started Jul 18 04:42:11 PM PDT 24
Finished Jul 18 04:42:15 PM PDT 24
Peak memory 196920 kb
Host smart-ccde8dc5-8064-4b83-a8d8-0c709f017abe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660870715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.660870715
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.303197878
Short name T515
Test name
Test status
Simulation time 122170755 ps
CPU time 0.97 seconds
Started Jul 18 04:42:11 PM PDT 24
Finished Jul 18 04:42:15 PM PDT 24
Peak memory 193384 kb
Host smart-70e29a57-884b-4e6f-95a7-732261a15cca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303197878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.303197878
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2325100713
Short name T478
Test name
Test status
Simulation time 101125509 ps
CPU time 0.94 seconds
Started Jul 18 04:42:07 PM PDT 24
Finished Jul 18 04:42:12 PM PDT 24
Peak memory 196036 kb
Host smart-c1a2666f-80a1-42a4-9f1f-ca408d29c870
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325100713 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2325100713
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1865010807
Short name T553
Test name
Test status
Simulation time 15283134 ps
CPU time 0.58 seconds
Started Jul 18 04:42:20 PM PDT 24
Finished Jul 18 04:42:23 PM PDT 24
Peak memory 182368 kb
Host smart-63840bb3-829c-405c-ac73-9032165b6b54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865010807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1865010807
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2275254548
Short name T572
Test name
Test status
Simulation time 37630043 ps
CPU time 0.56 seconds
Started Jul 18 04:42:20 PM PDT 24
Finished Jul 18 04:42:23 PM PDT 24
Peak memory 182232 kb
Host smart-504faef1-fe93-48d0-a364-4bfc005c1dff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275254548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2275254548
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2540024245
Short name T577
Test name
Test status
Simulation time 30119379 ps
CPU time 0.74 seconds
Started Jul 18 04:42:16 PM PDT 24
Finished Jul 18 04:42:20 PM PDT 24
Peak memory 191736 kb
Host smart-00bad85a-e12b-4d3e-96cd-a1d5ce400bfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540024245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2540024245
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3840456656
Short name T508
Test name
Test status
Simulation time 48313208 ps
CPU time 2.39 seconds
Started Jul 18 04:42:18 PM PDT 24
Finished Jul 18 04:42:24 PM PDT 24
Peak memory 197072 kb
Host smart-a7d4972b-beaa-455e-b1e6-3c79b847e476
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840456656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3840456656
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3355727526
Short name T528
Test name
Test status
Simulation time 47073789 ps
CPU time 0.84 seconds
Started Jul 18 04:42:06 PM PDT 24
Finished Jul 18 04:42:11 PM PDT 24
Peak memory 193780 kb
Host smart-c1d7a390-44ac-4be9-9b20-b3533d68f2dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355727526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.3355727526
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1389129973
Short name T91
Test name
Test status
Simulation time 36330765 ps
CPU time 1.41 seconds
Started Jul 18 04:41:46 PM PDT 24
Finished Jul 18 04:41:49 PM PDT 24
Peak memory 192364 kb
Host smart-97666a35-e821-402e-944e-9bb15de9ebea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389129973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1389129973
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3251585310
Short name T527
Test name
Test status
Simulation time 12424520 ps
CPU time 0.57 seconds
Started Jul 18 04:41:43 PM PDT 24
Finished Jul 18 04:41:45 PM PDT 24
Peak memory 182348 kb
Host smart-dffd0cd5-3a08-4cd9-8204-3b41457c6ccf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251585310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3251585310
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3811318720
Short name T492
Test name
Test status
Simulation time 27598798 ps
CPU time 1.04 seconds
Started Jul 18 04:41:45 PM PDT 24
Finished Jul 18 04:41:47 PM PDT 24
Peak memory 197068 kb
Host smart-05f253dd-682d-404a-9ea0-007e3159b346
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811318720 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3811318720
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2967749944
Short name T31
Test name
Test status
Simulation time 42531244 ps
CPU time 0.57 seconds
Started Jul 18 04:41:49 PM PDT 24
Finished Jul 18 04:41:51 PM PDT 24
Peak memory 182344 kb
Host smart-dc23d6c0-353c-4dd1-ab8a-fb6781769816
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967749944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2967749944
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1271593020
Short name T541
Test name
Test status
Simulation time 33920871 ps
CPU time 0.56 seconds
Started Jul 18 04:41:39 PM PDT 24
Finished Jul 18 04:41:41 PM PDT 24
Peak memory 182212 kb
Host smart-206e85e7-d887-41d7-a847-6dd37f943307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271593020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1271593020
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3143184379
Short name T545
Test name
Test status
Simulation time 16937254 ps
CPU time 0.68 seconds
Started Jul 18 04:41:38 PM PDT 24
Finished Jul 18 04:41:41 PM PDT 24
Peak memory 192656 kb
Host smart-884c8ec2-52a8-476b-8766-bc6ca92bcb73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143184379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3143184379
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3186681499
Short name T454
Test name
Test status
Simulation time 228345226 ps
CPU time 1.39 seconds
Started Jul 18 04:41:50 PM PDT 24
Finished Jul 18 04:41:53 PM PDT 24
Peak memory 197076 kb
Host smart-a3f7a8f9-180a-4d5f-b24e-bd7aeaec0e9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186681499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3186681499
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2842003552
Short name T107
Test name
Test status
Simulation time 45774129 ps
CPU time 0.9 seconds
Started Jul 18 04:41:38 PM PDT 24
Finished Jul 18 04:41:41 PM PDT 24
Peak memory 182796 kb
Host smart-215bb849-327a-4e0f-8c39-c4248b2dad27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842003552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2842003552
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.539919585
Short name T510
Test name
Test status
Simulation time 54752146 ps
CPU time 0.57 seconds
Started Jul 18 04:42:11 PM PDT 24
Finished Jul 18 04:42:15 PM PDT 24
Peak memory 182280 kb
Host smart-9533a9a3-40a2-4c5c-a5ad-5734fdeb4e6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539919585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.539919585
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1903504660
Short name T482
Test name
Test status
Simulation time 52828445 ps
CPU time 0.56 seconds
Started Jul 18 04:42:17 PM PDT 24
Finished Jul 18 04:42:21 PM PDT 24
Peak memory 182264 kb
Host smart-47a77229-ea8a-41a6-b846-bb5624657ab1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903504660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1903504660
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3305589115
Short name T453
Test name
Test status
Simulation time 21335404 ps
CPU time 0.54 seconds
Started Jul 18 04:42:11 PM PDT 24
Finished Jul 18 04:42:15 PM PDT 24
Peak memory 181740 kb
Host smart-e4cfa1f0-8850-4f6f-ae56-843660fbed49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305589115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3305589115
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.4185077204
Short name T561
Test name
Test status
Simulation time 47874747 ps
CPU time 0.57 seconds
Started Jul 18 04:42:12 PM PDT 24
Finished Jul 18 04:42:16 PM PDT 24
Peak memory 182192 kb
Host smart-248ee924-a137-4a41-ae94-bb9596899b3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185077204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.4185077204
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.216929815
Short name T451
Test name
Test status
Simulation time 16711507 ps
CPU time 0.6 seconds
Started Jul 18 04:42:13 PM PDT 24
Finished Jul 18 04:42:16 PM PDT 24
Peak memory 182256 kb
Host smart-53993ed8-ac5a-4bd6-b050-6920f3f4bc41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216929815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.216929815
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.389745107
Short name T457
Test name
Test status
Simulation time 29692834 ps
CPU time 0.54 seconds
Started Jul 18 04:42:16 PM PDT 24
Finished Jul 18 04:42:20 PM PDT 24
Peak memory 181920 kb
Host smart-ec47562f-cdd7-4565-932d-269f9c6a6ecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389745107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.389745107
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1674460137
Short name T465
Test name
Test status
Simulation time 17148324 ps
CPU time 0.57 seconds
Started Jul 18 04:42:14 PM PDT 24
Finished Jul 18 04:42:18 PM PDT 24
Peak memory 182264 kb
Host smart-4c4b2340-1dbb-476d-b4d0-e4ce4f95600a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674460137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1674460137
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2873933188
Short name T550
Test name
Test status
Simulation time 44723964 ps
CPU time 0.59 seconds
Started Jul 18 04:42:16 PM PDT 24
Finished Jul 18 04:42:20 PM PDT 24
Peak memory 181916 kb
Host smart-fbb5894c-a542-4974-a2dc-7e0dfea2b71a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873933188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2873933188
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2209224947
Short name T461
Test name
Test status
Simulation time 17724805 ps
CPU time 0.58 seconds
Started Jul 18 04:42:16 PM PDT 24
Finished Jul 18 04:42:20 PM PDT 24
Peak memory 181924 kb
Host smart-4d2bab94-8e79-4e62-a3bc-b7c914039260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209224947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2209224947
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1199016062
Short name T514
Test name
Test status
Simulation time 18126593 ps
CPU time 0.53 seconds
Started Jul 18 04:42:16 PM PDT 24
Finished Jul 18 04:42:20 PM PDT 24
Peak memory 182244 kb
Host smart-9afbd385-fcf7-4fb6-bdae-59a91099afbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199016062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1199016062
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2614557941
Short name T507
Test name
Test status
Simulation time 24082437 ps
CPU time 0.71 seconds
Started Jul 18 04:41:40 PM PDT 24
Finished Jul 18 04:41:43 PM PDT 24
Peak memory 182328 kb
Host smart-c03beaf7-9f01-414f-9be3-a54f477bb36f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614557941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2614557941
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1873151719
Short name T82
Test name
Test status
Simulation time 38177654 ps
CPU time 1.39 seconds
Started Jul 18 04:41:52 PM PDT 24
Finished Jul 18 04:41:56 PM PDT 24
Peak memory 192752 kb
Host smart-a98129de-7838-438f-9db1-bb3551ebbc46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873151719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1873151719
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1042928698
Short name T90
Test name
Test status
Simulation time 12982762 ps
CPU time 0.55 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:01 PM PDT 24
Peak memory 182364 kb
Host smart-51bc126b-25c8-4dc6-a494-f8fee73d83cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042928698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1042928698
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2366220450
Short name T463
Test name
Test status
Simulation time 127432009 ps
CPU time 0.97 seconds
Started Jul 18 04:41:41 PM PDT 24
Finished Jul 18 04:41:44 PM PDT 24
Peak memory 197008 kb
Host smart-d6942efb-8902-418f-b892-3041c5c366e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366220450 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2366220450
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1263930408
Short name T88
Test name
Test status
Simulation time 13047501 ps
CPU time 0.59 seconds
Started Jul 18 04:41:43 PM PDT 24
Finished Jul 18 04:41:45 PM PDT 24
Peak memory 182744 kb
Host smart-ba78d82e-3699-4e1e-bd43-309b84a0d57f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263930408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1263930408
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.716360752
Short name T523
Test name
Test status
Simulation time 17554118 ps
CPU time 0.62 seconds
Started Jul 18 04:41:39 PM PDT 24
Finished Jul 18 04:41:41 PM PDT 24
Peak memory 182316 kb
Host smart-42821d17-5b61-4af5-88b7-382e4dec6df0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716360752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.716360752
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2414932122
Short name T558
Test name
Test status
Simulation time 25954287 ps
CPU time 0.71 seconds
Started Jul 18 04:41:44 PM PDT 24
Finished Jul 18 04:41:46 PM PDT 24
Peak memory 191712 kb
Host smart-b0ed6c09-66ca-4d4e-a3c0-4f3a9cc65a02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414932122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2414932122
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.530650461
Short name T489
Test name
Test status
Simulation time 361405981 ps
CPU time 1.45 seconds
Started Jul 18 04:41:41 PM PDT 24
Finished Jul 18 04:41:44 PM PDT 24
Peak memory 197012 kb
Host smart-276f9c02-f4cc-4ecb-ad69-b96a6bff8290
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530650461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.530650461
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3724006487
Short name T28
Test name
Test status
Simulation time 101807355 ps
CPU time 1.09 seconds
Started Jul 18 04:41:31 PM PDT 24
Finished Jul 18 04:41:33 PM PDT 24
Peak memory 194832 kb
Host smart-6231d8a8-6abb-4e6e-9b85-bb2f1f85ce82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724006487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3724006487
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2209740633
Short name T476
Test name
Test status
Simulation time 17005960 ps
CPU time 0.57 seconds
Started Jul 18 04:42:13 PM PDT 24
Finished Jul 18 04:42:17 PM PDT 24
Peak memory 182200 kb
Host smart-1a6de44c-7fac-4d02-b9c1-f7e22bf9ac22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209740633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2209740633
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4248614941
Short name T526
Test name
Test status
Simulation time 27054262 ps
CPU time 0.59 seconds
Started Jul 18 04:42:15 PM PDT 24
Finished Jul 18 04:42:19 PM PDT 24
Peak memory 182188 kb
Host smart-133e9892-29f0-49ed-9f69-e485a491f03b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248614941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.4248614941
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1776425768
Short name T571
Test name
Test status
Simulation time 11735421 ps
CPU time 0.56 seconds
Started Jul 18 04:42:11 PM PDT 24
Finished Jul 18 04:42:14 PM PDT 24
Peak memory 182252 kb
Host smart-402e3618-c1f6-40c5-99ba-8d60d894a0a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776425768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1776425768
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.990441699
Short name T557
Test name
Test status
Simulation time 48044411 ps
CPU time 0.55 seconds
Started Jul 18 04:42:17 PM PDT 24
Finished Jul 18 04:42:21 PM PDT 24
Peak memory 182236 kb
Host smart-be97f98d-a27e-4c6f-977b-928e28337db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990441699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.990441699
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2018941096
Short name T547
Test name
Test status
Simulation time 44795260 ps
CPU time 0.54 seconds
Started Jul 18 04:42:19 PM PDT 24
Finished Jul 18 04:42:22 PM PDT 24
Peak memory 182264 kb
Host smart-c17910da-2346-46ba-9871-7788b05fd909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018941096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2018941096
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3762796374
Short name T471
Test name
Test status
Simulation time 49452736 ps
CPU time 0.6 seconds
Started Jul 18 04:42:17 PM PDT 24
Finished Jul 18 04:42:21 PM PDT 24
Peak memory 182664 kb
Host smart-654f2f09-7efa-4ae4-a1ef-2599c59e6b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762796374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3762796374
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1201620154
Short name T540
Test name
Test status
Simulation time 24836991 ps
CPU time 0.57 seconds
Started Jul 18 04:42:09 PM PDT 24
Finished Jul 18 04:42:12 PM PDT 24
Peak memory 182180 kb
Host smart-7a1cbc77-d64b-4fad-b1f6-a933888db21e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201620154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1201620154
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2288982696
Short name T458
Test name
Test status
Simulation time 15126871 ps
CPU time 0.53 seconds
Started Jul 18 04:42:12 PM PDT 24
Finished Jul 18 04:42:16 PM PDT 24
Peak memory 182236 kb
Host smart-e4b9f39f-222e-45a3-9e4d-14f35516e013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288982696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2288982696
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3686672720
Short name T568
Test name
Test status
Simulation time 13263796 ps
CPU time 0.54 seconds
Started Jul 18 04:42:16 PM PDT 24
Finished Jul 18 04:42:19 PM PDT 24
Peak memory 181724 kb
Host smart-abe405af-3345-47f7-9651-c87899f2f4e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686672720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3686672720
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.839121122
Short name T472
Test name
Test status
Simulation time 44339898 ps
CPU time 0.57 seconds
Started Jul 18 04:42:23 PM PDT 24
Finished Jul 18 04:42:24 PM PDT 24
Peak memory 182240 kb
Host smart-4896a868-eb33-41b4-951e-e9ad6d874a40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839121122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.839121122
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3176581464
Short name T93
Test name
Test status
Simulation time 14459427 ps
CPU time 0.71 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:01 PM PDT 24
Peak memory 191552 kb
Host smart-3e5d7e3c-5722-482a-8214-98e5d048bc62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176581464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3176581464
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.61695958
Short name T563
Test name
Test status
Simulation time 142662768 ps
CPU time 1.43 seconds
Started Jul 18 04:41:51 PM PDT 24
Finished Jul 18 04:41:54 PM PDT 24
Peak memory 192400 kb
Host smart-53227159-f7bf-4345-aa06-30bd63606123
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61695958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ba
sh.61695958
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2212628216
Short name T47
Test name
Test status
Simulation time 275875945 ps
CPU time 0.57 seconds
Started Jul 18 04:41:52 PM PDT 24
Finished Jul 18 04:41:55 PM PDT 24
Peak memory 182736 kb
Host smart-68f75f30-288d-4e1f-9258-80cc6a0be533
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212628216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2212628216
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2592816528
Short name T562
Test name
Test status
Simulation time 23031718 ps
CPU time 0.66 seconds
Started Jul 18 04:41:55 PM PDT 24
Finished Jul 18 04:42:00 PM PDT 24
Peak memory 193800 kb
Host smart-7adb782c-bf88-41f0-84d6-461df3c463a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592816528 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2592816528
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1600511710
Short name T87
Test name
Test status
Simulation time 22457496 ps
CPU time 0.59 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:01 PM PDT 24
Peak memory 182344 kb
Host smart-3cba3b22-2f63-4217-97c9-db29c6d24a9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600511710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1600511710
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2339846838
Short name T517
Test name
Test status
Simulation time 18771736 ps
CPU time 0.59 seconds
Started Jul 18 04:41:50 PM PDT 24
Finished Jul 18 04:41:52 PM PDT 24
Peak memory 182232 kb
Host smart-4b76f5dc-809c-4f29-8481-1f9bd58909b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339846838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2339846838
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1602502864
Short name T524
Test name
Test status
Simulation time 31868955 ps
CPU time 0.74 seconds
Started Jul 18 04:42:03 PM PDT 24
Finished Jul 18 04:42:07 PM PDT 24
Peak memory 192956 kb
Host smart-004875f6-1993-4a03-8b33-06168ab757a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602502864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1602502864
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2373384317
Short name T534
Test name
Test status
Simulation time 140380074 ps
CPU time 1.47 seconds
Started Jul 18 04:41:38 PM PDT 24
Finished Jul 18 04:41:42 PM PDT 24
Peak memory 197092 kb
Host smart-175d9804-766f-4e01-b70f-75954755d006
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373384317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2373384317
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1267606847
Short name T512
Test name
Test status
Simulation time 87633589 ps
CPU time 0.79 seconds
Started Jul 18 04:41:54 PM PDT 24
Finished Jul 18 04:41:58 PM PDT 24
Peak memory 182616 kb
Host smart-4234a31b-1f26-4377-bb8a-fe212f90e557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267606847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1267606847
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.21527503
Short name T470
Test name
Test status
Simulation time 55200490 ps
CPU time 0.56 seconds
Started Jul 18 04:42:18 PM PDT 24
Finished Jul 18 04:42:22 PM PDT 24
Peak memory 182620 kb
Host smart-cbf503c5-30a6-4db0-b21a-28cca514ea69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21527503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.21527503
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3315735970
Short name T466
Test name
Test status
Simulation time 12895068 ps
CPU time 0.53 seconds
Started Jul 18 04:42:13 PM PDT 24
Finished Jul 18 04:42:17 PM PDT 24
Peak memory 181904 kb
Host smart-40978291-e371-433e-a2e3-83b985be0c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315735970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3315735970
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1512210835
Short name T537
Test name
Test status
Simulation time 39402885 ps
CPU time 0.58 seconds
Started Jul 18 04:42:13 PM PDT 24
Finished Jul 18 04:42:17 PM PDT 24
Peak memory 182304 kb
Host smart-32d78e36-4337-4ac7-924c-2027e36f1726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512210835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1512210835
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3064873931
Short name T552
Test name
Test status
Simulation time 71355523 ps
CPU time 0.61 seconds
Started Jul 18 04:42:17 PM PDT 24
Finished Jul 18 04:42:21 PM PDT 24
Peak memory 182192 kb
Host smart-71f50688-554b-464d-bbc4-68f666fa8c81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064873931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3064873931
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2983351118
Short name T542
Test name
Test status
Simulation time 12993663 ps
CPU time 0.56 seconds
Started Jul 18 04:42:14 PM PDT 24
Finished Jul 18 04:42:18 PM PDT 24
Peak memory 182268 kb
Host smart-b14a72e1-9b30-4ffb-9df4-6e8ed99008f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983351118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2983351118
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3156216071
Short name T538
Test name
Test status
Simulation time 21393746 ps
CPU time 0.59 seconds
Started Jul 18 04:42:10 PM PDT 24
Finished Jul 18 04:42:14 PM PDT 24
Peak memory 182240 kb
Host smart-d7a57187-bcf5-4ad2-b2ac-fd77c87add89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156216071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3156216071
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1753747143
Short name T452
Test name
Test status
Simulation time 28127798 ps
CPU time 0.55 seconds
Started Jul 18 04:42:10 PM PDT 24
Finished Jul 18 04:42:13 PM PDT 24
Peak memory 182244 kb
Host smart-14a82375-48ec-4824-a45d-1ae26f5d5246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753747143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1753747143
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2416112961
Short name T455
Test name
Test status
Simulation time 52739740 ps
CPU time 0.6 seconds
Started Jul 18 04:42:05 PM PDT 24
Finished Jul 18 04:42:10 PM PDT 24
Peak memory 182260 kb
Host smart-af061baf-d5bd-4ad6-bf98-0e34d43c0205
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416112961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2416112961
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3296562568
Short name T543
Test name
Test status
Simulation time 59654985 ps
CPU time 0.54 seconds
Started Jul 18 04:42:16 PM PDT 24
Finished Jul 18 04:42:20 PM PDT 24
Peak memory 182192 kb
Host smart-8df9f242-b923-429e-8e8e-439d63537357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296562568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3296562568
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2555906606
Short name T516
Test name
Test status
Simulation time 17199680 ps
CPU time 0.57 seconds
Started Jul 18 04:42:15 PM PDT 24
Finished Jul 18 04:42:19 PM PDT 24
Peak memory 182252 kb
Host smart-57b407aa-dea0-4c6c-8a05-023964106213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555906606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2555906606
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1286660448
Short name T555
Test name
Test status
Simulation time 79776615 ps
CPU time 1.08 seconds
Started Jul 18 04:42:00 PM PDT 24
Finished Jul 18 04:42:05 PM PDT 24
Peak memory 197052 kb
Host smart-d3c2fc18-1c0c-49b2-8f94-08165108b510
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286660448 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1286660448
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2423837139
Short name T565
Test name
Test status
Simulation time 18541644 ps
CPU time 0.61 seconds
Started Jul 18 04:41:53 PM PDT 24
Finished Jul 18 04:41:57 PM PDT 24
Peak memory 182364 kb
Host smart-d5c08dc9-d4b5-47bc-8bae-916482a37642
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423837139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2423837139
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1394262925
Short name T494
Test name
Test status
Simulation time 46169806 ps
CPU time 0.58 seconds
Started Jul 18 04:41:51 PM PDT 24
Finished Jul 18 04:41:53 PM PDT 24
Peak memory 181800 kb
Host smart-00592ede-7cdc-44b0-8f01-2b9185472858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394262925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1394262925
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2615285859
Short name T94
Test name
Test status
Simulation time 79035751 ps
CPU time 0.84 seconds
Started Jul 18 04:41:53 PM PDT 24
Finished Jul 18 04:41:57 PM PDT 24
Peak memory 193072 kb
Host smart-8713e8f7-4154-42da-9f44-9773c0882cbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615285859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2615285859
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3582681287
Short name T467
Test name
Test status
Simulation time 638633999 ps
CPU time 1.44 seconds
Started Jul 18 04:41:51 PM PDT 24
Finished Jul 18 04:41:54 PM PDT 24
Peak memory 197076 kb
Host smart-2bceebe0-a05e-4827-8582-3174fd249752
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582681287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3582681287
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3338564777
Short name T109
Test name
Test status
Simulation time 142465779 ps
CPU time 1.18 seconds
Started Jul 18 04:41:52 PM PDT 24
Finished Jul 18 04:41:56 PM PDT 24
Peak memory 193728 kb
Host smart-01cb102c-663a-427f-81a6-3c2ff109e8f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338564777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3338564777
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.588459602
Short name T574
Test name
Test status
Simulation time 47358358 ps
CPU time 1.23 seconds
Started Jul 18 04:41:58 PM PDT 24
Finished Jul 18 04:42:04 PM PDT 24
Peak memory 197504 kb
Host smart-869a2bf5-33bd-4f2f-bc5c-91eda89cd196
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588459602 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.588459602
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1398769557
Short name T503
Test name
Test status
Simulation time 29022802 ps
CPU time 0.55 seconds
Started Jul 18 04:41:55 PM PDT 24
Finished Jul 18 04:41:59 PM PDT 24
Peak memory 182260 kb
Host smart-82583e5e-09e5-41e4-a7f5-1853ac1c83f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398769557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1398769557
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2900178731
Short name T502
Test name
Test status
Simulation time 17065392 ps
CPU time 0.57 seconds
Started Jul 18 04:41:52 PM PDT 24
Finished Jul 18 04:41:55 PM PDT 24
Peak memory 182228 kb
Host smart-db66ede6-a5d8-4199-9388-2e9c7e27c744
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900178731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2900178731
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3726193316
Short name T559
Test name
Test status
Simulation time 114269532 ps
CPU time 0.64 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:01 PM PDT 24
Peak memory 192152 kb
Host smart-c4423bdb-b062-460d-a8d0-75cdd4cbc0d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726193316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3726193316
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.353029154
Short name T532
Test name
Test status
Simulation time 544611705 ps
CPU time 2.57 seconds
Started Jul 18 04:41:55 PM PDT 24
Finished Jul 18 04:42:01 PM PDT 24
Peak memory 197092 kb
Host smart-64f4df0f-c083-4b5c-a142-1c8ddb3b2e1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353029154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.353029154
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.19178006
Short name T522
Test name
Test status
Simulation time 79395949 ps
CPU time 1.11 seconds
Started Jul 18 04:41:52 PM PDT 24
Finished Jul 18 04:41:56 PM PDT 24
Peak memory 183344 kb
Host smart-77243b33-8769-47ad-90a4-8aae8792c8a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19178006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg
_err.19178006
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2939443499
Short name T462
Test name
Test status
Simulation time 76604080 ps
CPU time 1.09 seconds
Started Jul 18 04:41:52 PM PDT 24
Finished Jul 18 04:41:55 PM PDT 24
Peak memory 196988 kb
Host smart-1df75c95-b241-453f-affa-de013cd61a0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939443499 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2939443499
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.14867748
Short name T60
Test name
Test status
Simulation time 22768353 ps
CPU time 0.55 seconds
Started Jul 18 04:41:59 PM PDT 24
Finished Jul 18 04:42:04 PM PDT 24
Peak memory 182344 kb
Host smart-ad427c8f-f22a-4997-9816-990c8bafabd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14867748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.14867748
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1986720694
Short name T560
Test name
Test status
Simulation time 10972240 ps
CPU time 0.51 seconds
Started Jul 18 04:41:54 PM PDT 24
Finished Jul 18 04:41:58 PM PDT 24
Peak memory 181720 kb
Host smart-33552976-1afa-487b-adb1-23a9d7e1018e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986720694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1986720694
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3890531063
Short name T46
Test name
Test status
Simulation time 79282561 ps
CPU time 0.64 seconds
Started Jul 18 04:41:51 PM PDT 24
Finished Jul 18 04:41:53 PM PDT 24
Peak memory 191252 kb
Host smart-24ec4333-aa6e-4e06-8fc9-e0ad19ab71c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890531063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3890531063
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1521179467
Short name T456
Test name
Test status
Simulation time 115156625 ps
CPU time 1.39 seconds
Started Jul 18 04:41:54 PM PDT 24
Finished Jul 18 04:41:59 PM PDT 24
Peak memory 196828 kb
Host smart-29470d05-8244-4497-a256-8955a7cd1fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521179467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1521179467
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.991499707
Short name T549
Test name
Test status
Simulation time 217093322 ps
CPU time 0.86 seconds
Started Jul 18 04:41:55 PM PDT 24
Finished Jul 18 04:41:59 PM PDT 24
Peak memory 182668 kb
Host smart-cec4e999-e46a-4d0c-9820-f68330562344
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991499707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.991499707
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4294925089
Short name T544
Test name
Test status
Simulation time 23661139 ps
CPU time 1.1 seconds
Started Jul 18 04:42:00 PM PDT 24
Finished Jul 18 04:42:05 PM PDT 24
Peak memory 197052 kb
Host smart-9e0d7cf3-bc03-4fb0-b6a2-bcb5df766366
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294925089 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.4294925089
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3908730394
Short name T86
Test name
Test status
Simulation time 15170242 ps
CPU time 0.58 seconds
Started Jul 18 04:41:52 PM PDT 24
Finished Jul 18 04:41:55 PM PDT 24
Peak memory 182348 kb
Host smart-63d86255-5d59-4c86-8bd9-fff5a69d8bda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908730394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3908730394
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3443606535
Short name T496
Test name
Test status
Simulation time 18041517 ps
CPU time 0.53 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:00 PM PDT 24
Peak memory 181748 kb
Host smart-25807e1b-e570-45b6-9984-2293e134095f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443606535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3443606535
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1134181752
Short name T506
Test name
Test status
Simulation time 20122954 ps
CPU time 0.81 seconds
Started Jul 18 04:41:57 PM PDT 24
Finished Jul 18 04:42:02 PM PDT 24
Peak memory 191332 kb
Host smart-38364dd9-2a39-4d90-88bd-816b787a56ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134181752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1134181752
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3519002827
Short name T477
Test name
Test status
Simulation time 219312638 ps
CPU time 3.02 seconds
Started Jul 18 04:41:54 PM PDT 24
Finished Jul 18 04:42:01 PM PDT 24
Peak memory 197124 kb
Host smart-89156051-bfdf-4806-acf9-e64420827073
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519002827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3519002827
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1331192202
Short name T48
Test name
Test status
Simulation time 126975773 ps
CPU time 1.38 seconds
Started Jul 18 04:41:52 PM PDT 24
Finished Jul 18 04:41:55 PM PDT 24
Peak memory 181884 kb
Host smart-d106e406-aaf2-42b3-bffb-e32f87cd1ec3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331192202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1331192202
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2847071629
Short name T460
Test name
Test status
Simulation time 41010064 ps
CPU time 0.91 seconds
Started Jul 18 04:41:56 PM PDT 24
Finished Jul 18 04:42:02 PM PDT 24
Peak memory 196988 kb
Host smart-fd53a3b3-2d78-4aa2-b8c2-af301e3c4c20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847071629 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2847071629
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.780987177
Short name T83
Test name
Test status
Simulation time 14642188 ps
CPU time 0.58 seconds
Started Jul 18 04:41:54 PM PDT 24
Finished Jul 18 04:41:59 PM PDT 24
Peak memory 182344 kb
Host smart-85a3f591-f047-466f-8cba-742c1b6c0c49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780987177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.780987177
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4059684786
Short name T473
Test name
Test status
Simulation time 43641108 ps
CPU time 0.56 seconds
Started Jul 18 04:41:52 PM PDT 24
Finished Jul 18 04:41:55 PM PDT 24
Peak memory 181720 kb
Host smart-a48aae7e-10c4-407a-9e64-ca83e81412e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059684786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.4059684786
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3919758311
Short name T95
Test name
Test status
Simulation time 23908072 ps
CPU time 0.63 seconds
Started Jul 18 04:41:55 PM PDT 24
Finished Jul 18 04:42:00 PM PDT 24
Peak memory 191600 kb
Host smart-b2d550db-829b-4761-a403-46353d85b737
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919758311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3919758311
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1155852915
Short name T500
Test name
Test status
Simulation time 125092807 ps
CPU time 1.61 seconds
Started Jul 18 04:41:58 PM PDT 24
Finished Jul 18 04:42:04 PM PDT 24
Peak memory 197084 kb
Host smart-366a03a7-be5e-4d85-a47a-e768ed34893b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155852915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1155852915
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.950016030
Short name T30
Test name
Test status
Simulation time 574169707 ps
CPU time 1.5 seconds
Started Jul 18 04:41:59 PM PDT 24
Finished Jul 18 04:42:05 PM PDT 24
Peak memory 194936 kb
Host smart-d65a8d97-cb0a-4c71-b063-0d541084e081
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950016030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.950016030
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2067808149
Short name T78
Test name
Test status
Simulation time 106584539369 ps
CPU time 100.51 seconds
Started Jul 18 04:42:23 PM PDT 24
Finished Jul 18 04:44:05 PM PDT 24
Peak memory 183340 kb
Host smart-81a9a889-cd2b-4f71-91b5-63c145002ca0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067808149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2067808149
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2041178201
Short name T421
Test name
Test status
Simulation time 74067988542 ps
CPU time 105.41 seconds
Started Jul 18 04:42:16 PM PDT 24
Finished Jul 18 04:44:05 PM PDT 24
Peak memory 183376 kb
Host smart-64179e73-037f-4b69-9c0a-38f2a613eb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041178201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2041178201
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.3360296599
Short name T409
Test name
Test status
Simulation time 123331941896 ps
CPU time 61.98 seconds
Started Jul 18 04:42:17 PM PDT 24
Finished Jul 18 04:43:23 PM PDT 24
Peak memory 183360 kb
Host smart-1375778f-b03e-4025-b86c-3aa3494d336f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360296599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3360296599
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.417278274
Short name T24
Test name
Test status
Simulation time 15917082974 ps
CPU time 29.62 seconds
Started Jul 18 04:42:14 PM PDT 24
Finished Jul 18 04:42:47 PM PDT 24
Peak memory 191580 kb
Host smart-2511d28c-980c-42d2-b71f-819cbd984b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417278274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.417278274
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1071320441
Short name T15
Test name
Test status
Simulation time 31119568 ps
CPU time 0.73 seconds
Started Jul 18 04:42:17 PM PDT 24
Finished Jul 18 04:42:21 PM PDT 24
Peak memory 214484 kb
Host smart-806f0dc2-7a4c-413e-a152-be06c2d5202a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071320441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1071320441
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.4022586573
Short name T146
Test name
Test status
Simulation time 385982880717 ps
CPU time 314.28 seconds
Started Jul 18 04:42:09 PM PDT 24
Finished Jul 18 04:47:27 PM PDT 24
Peak memory 183360 kb
Host smart-e6d1d0e1-b9b4-456e-ac02-75f0023e31de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022586573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.4022586573
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2625937360
Short name T105
Test name
Test status
Simulation time 445511877271 ps
CPU time 110.58 seconds
Started Jul 18 04:42:23 PM PDT 24
Finished Jul 18 04:44:14 PM PDT 24
Peak memory 183364 kb
Host smart-bedc94a6-6568-4fb5-a3bf-53037e45c2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625937360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2625937360
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3833279440
Short name T104
Test name
Test status
Simulation time 334990222633 ps
CPU time 979.63 seconds
Started Jul 18 04:42:15 PM PDT 24
Finished Jul 18 04:58:38 PM PDT 24
Peak memory 183400 kb
Host smart-7c928fa3-65dc-4350-9388-a4bbe4288d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833279440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3833279440
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3995154353
Short name T16
Test name
Test status
Simulation time 83702110 ps
CPU time 0.93 seconds
Started Jul 18 04:42:21 PM PDT 24
Finished Jul 18 04:42:24 PM PDT 24
Peak memory 214720 kb
Host smart-d82a6cde-4bd4-4eac-afc0-64257517a159
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995154353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3995154353
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.4186096549
Short name T402
Test name
Test status
Simulation time 564901934543 ps
CPU time 231.42 seconds
Started Jul 18 04:42:31 PM PDT 24
Finished Jul 18 04:46:24 PM PDT 24
Peak memory 183344 kb
Host smart-cddc687e-e87c-4ca5-82c8-b499c0f88a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186096549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.4186096549
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1258829205
Short name T124
Test name
Test status
Simulation time 58430189304 ps
CPU time 250.71 seconds
Started Jul 18 04:42:38 PM PDT 24
Finished Jul 18 04:46:52 PM PDT 24
Peak memory 191592 kb
Host smart-303273e1-1bda-4910-bc3e-0a309435e6d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258829205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1258829205
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1042008989
Short name T229
Test name
Test status
Simulation time 47515405124 ps
CPU time 40.17 seconds
Started Jul 18 04:42:31 PM PDT 24
Finished Jul 18 04:43:13 PM PDT 24
Peak memory 183364 kb
Host smart-71f7440a-79a3-4362-88ea-dcbca260ac4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042008989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1042008989
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2355407832
Short name T145
Test name
Test status
Simulation time 262623828855 ps
CPU time 342.85 seconds
Started Jul 18 04:42:36 PM PDT 24
Finished Jul 18 04:48:19 PM PDT 24
Peak memory 191604 kb
Host smart-7dbe39d9-38b6-43d1-b94e-64bc9bc664e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355407832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2355407832
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.2622649117
Short name T167
Test name
Test status
Simulation time 153006205334 ps
CPU time 845.95 seconds
Started Jul 18 04:43:57 PM PDT 24
Finished Jul 18 04:58:04 PM PDT 24
Peak memory 191292 kb
Host smart-95232330-d9e6-4545-a70b-897be78762c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622649117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2622649117
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2470342882
Short name T235
Test name
Test status
Simulation time 252717333494 ps
CPU time 253.9 seconds
Started Jul 18 04:43:31 PM PDT 24
Finished Jul 18 04:47:48 PM PDT 24
Peak memory 195128 kb
Host smart-17fa7652-acd6-42c5-aa8a-cba0a7891cb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470342882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2470342882
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1852532431
Short name T316
Test name
Test status
Simulation time 45836478143 ps
CPU time 94.34 seconds
Started Jul 18 04:43:28 PM PDT 24
Finished Jul 18 04:45:06 PM PDT 24
Peak memory 191604 kb
Host smart-d9884cd8-36e5-4bcb-a4f5-ef7d5ef830c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852532431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1852532431
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2142834153
Short name T293
Test name
Test status
Simulation time 176485484160 ps
CPU time 76.39 seconds
Started Jul 18 04:44:02 PM PDT 24
Finished Jul 18 04:45:19 PM PDT 24
Peak memory 183092 kb
Host smart-5583782c-67d2-466b-bd46-20b5a4e7e030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142834153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2142834153
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1394421184
Short name T284
Test name
Test status
Simulation time 15696444500 ps
CPU time 9.61 seconds
Started Jul 18 04:43:30 PM PDT 24
Finished Jul 18 04:43:42 PM PDT 24
Peak memory 183396 kb
Host smart-5c7c99e9-a6d1-4559-b304-e7a915477daf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394421184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1394421184
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2242966673
Short name T25
Test name
Test status
Simulation time 182655431193 ps
CPU time 241.58 seconds
Started Jul 18 04:42:28 PM PDT 24
Finished Jul 18 04:46:32 PM PDT 24
Peak memory 183348 kb
Host smart-db2dea71-1b8e-45ef-87ef-64f97bda24f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242966673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2242966673
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.4083687375
Short name T238
Test name
Test status
Simulation time 344670124682 ps
CPU time 115.27 seconds
Started Jul 18 04:42:33 PM PDT 24
Finished Jul 18 04:44:29 PM PDT 24
Peak memory 191576 kb
Host smart-2b53f3e8-7e02-41ae-99ed-403d32ad093e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083687375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.4083687375
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.567602961
Short name T67
Test name
Test status
Simulation time 231288122752 ps
CPU time 615.12 seconds
Started Jul 18 04:42:37 PM PDT 24
Finished Jul 18 04:52:54 PM PDT 24
Peak memory 191564 kb
Host smart-a9e02a30-f75d-4c69-8c39-340a06ad60f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567602961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
567602961
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.2318303303
Short name T197
Test name
Test status
Simulation time 68219279490 ps
CPU time 107.93 seconds
Started Jul 18 04:43:33 PM PDT 24
Finished Jul 18 04:45:24 PM PDT 24
Peak memory 191292 kb
Host smart-2cad7ad6-c9dc-40dc-b471-316f96c15701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318303303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2318303303
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.4020571048
Short name T425
Test name
Test status
Simulation time 28673415945 ps
CPU time 49.11 seconds
Started Jul 18 04:43:34 PM PDT 24
Finished Jul 18 04:44:27 PM PDT 24
Peak memory 183076 kb
Host smart-75d1e3f7-abe2-40bb-8f30-50f6ffa3bff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020571048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.4020571048
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2238902594
Short name T314
Test name
Test status
Simulation time 22406599045 ps
CPU time 209.58 seconds
Started Jul 18 04:43:35 PM PDT 24
Finished Jul 18 04:47:08 PM PDT 24
Peak memory 183400 kb
Host smart-d72f29ee-1546-473e-8ddc-18cde0785927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238902594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2238902594
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.191783561
Short name T140
Test name
Test status
Simulation time 359850132545 ps
CPU time 468.62 seconds
Started Jul 18 04:43:34 PM PDT 24
Finished Jul 18 04:51:26 PM PDT 24
Peak memory 191556 kb
Host smart-b1902151-5447-4c7a-9558-6e202c06f854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191783561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.191783561
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1491937947
Short name T265
Test name
Test status
Simulation time 10314434203 ps
CPU time 17.44 seconds
Started Jul 18 04:42:35 PM PDT 24
Finished Jul 18 04:42:54 PM PDT 24
Peak memory 183348 kb
Host smart-36b50f38-cb44-410e-ae73-2f8e91640ce1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491937947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1491937947
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3662315792
Short name T431
Test name
Test status
Simulation time 91734375067 ps
CPU time 113.54 seconds
Started Jul 18 04:42:35 PM PDT 24
Finished Jul 18 04:44:30 PM PDT 24
Peak memory 183324 kb
Host smart-a432f18f-7327-48a6-9496-66c33b15a5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662315792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3662315792
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.2337065919
Short name T300
Test name
Test status
Simulation time 129874486040 ps
CPU time 90.67 seconds
Started Jul 18 04:42:37 PM PDT 24
Finished Jul 18 04:44:09 PM PDT 24
Peak memory 183356 kb
Host smart-d3f677c7-3aa4-440e-8892-6abb2ffa59f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337065919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2337065919
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.4278674742
Short name T267
Test name
Test status
Simulation time 32572750354 ps
CPU time 43.14 seconds
Started Jul 18 04:42:28 PM PDT 24
Finished Jul 18 04:43:13 PM PDT 24
Peak memory 183196 kb
Host smart-72be7c9c-a681-4d36-a407-6e8fcf51891d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278674742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.4278674742
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/123.rv_timer_random.4270431341
Short name T447
Test name
Test status
Simulation time 20054381819 ps
CPU time 198.96 seconds
Started Jul 18 04:43:17 PM PDT 24
Finished Jul 18 04:46:37 PM PDT 24
Peak memory 183368 kb
Host smart-a96ffdc7-7687-4875-a55c-4e4e49cc8380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270431341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.4270431341
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1007097384
Short name T118
Test name
Test status
Simulation time 414963884461 ps
CPU time 292 seconds
Started Jul 18 04:43:26 PM PDT 24
Finished Jul 18 04:48:21 PM PDT 24
Peak memory 191556 kb
Host smart-dc27c7d5-c249-484a-a5b1-e198611b10c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007097384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1007097384
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3064263180
Short name T230
Test name
Test status
Simulation time 561407321408 ps
CPU time 970.24 seconds
Started Jul 18 04:43:33 PM PDT 24
Finished Jul 18 04:59:47 PM PDT 24
Peak memory 191556 kb
Host smart-64d62367-af4f-4e48-9346-4bcf7971cb27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064263180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3064263180
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3349981447
Short name T441
Test name
Test status
Simulation time 40618347458 ps
CPU time 27.3 seconds
Started Jul 18 04:43:25 PM PDT 24
Finished Jul 18 04:43:56 PM PDT 24
Peak memory 183368 kb
Host smart-72e3305d-c29d-40b8-a6d3-a9d0fd5e2d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349981447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3349981447
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3510052526
Short name T309
Test name
Test status
Simulation time 174159370081 ps
CPU time 69.55 seconds
Started Jul 18 04:43:38 PM PDT 24
Finished Jul 18 04:44:50 PM PDT 24
Peak memory 183360 kb
Host smart-68403fc6-179e-4825-b67e-77fa7a78544a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510052526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3510052526
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.227890113
Short name T134
Test name
Test status
Simulation time 180925168052 ps
CPU time 236.4 seconds
Started Jul 18 04:43:35 PM PDT 24
Finished Jul 18 04:47:35 PM PDT 24
Peak memory 191580 kb
Host smart-cfda6108-3002-4b76-a455-84015565dc0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227890113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.227890113
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.691154560
Short name T416
Test name
Test status
Simulation time 54336638012 ps
CPU time 92.55 seconds
Started Jul 18 04:42:37 PM PDT 24
Finished Jul 18 04:44:12 PM PDT 24
Peak memory 183336 kb
Host smart-6191f39d-1357-4306-99df-9494eebb0cff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691154560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.691154560
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.485442420
Short name T3
Test name
Test status
Simulation time 216499668229 ps
CPU time 92.17 seconds
Started Jul 18 04:42:29 PM PDT 24
Finished Jul 18 04:44:03 PM PDT 24
Peak memory 183364 kb
Host smart-33659495-7440-4b09-9ac6-656ee7e9f87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485442420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.485442420
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.893008134
Short name T166
Test name
Test status
Simulation time 176803074952 ps
CPU time 307.04 seconds
Started Jul 18 04:42:39 PM PDT 24
Finished Jul 18 04:47:49 PM PDT 24
Peak memory 191548 kb
Host smart-3e906e32-77e1-400c-9206-751f7ce7df62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893008134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.893008134
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3424204561
Short name T381
Test name
Test status
Simulation time 151648113231 ps
CPU time 83.61 seconds
Started Jul 18 04:42:34 PM PDT 24
Finished Jul 18 04:43:59 PM PDT 24
Peak memory 191552 kb
Host smart-aa04ad08-c960-498a-9ae7-8910487ecb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424204561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3424204561
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2130683924
Short name T427
Test name
Test status
Simulation time 189128440181 ps
CPU time 80.67 seconds
Started Jul 18 04:42:37 PM PDT 24
Finished Jul 18 04:44:00 PM PDT 24
Peak memory 183348 kb
Host smart-96d157e2-b314-48d0-bab6-1e98077174b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130683924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2130683924
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.3970096010
Short name T39
Test name
Test status
Simulation time 296158325952 ps
CPU time 607.78 seconds
Started Jul 18 04:42:37 PM PDT 24
Finished Jul 18 04:52:46 PM PDT 24
Peak memory 209132 kb
Host smart-a38efdec-a874-4653-8851-ef404ea802c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970096010 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.3970096010
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.rv_timer_random.239094967
Short name T125
Test name
Test status
Simulation time 166030825685 ps
CPU time 853.43 seconds
Started Jul 18 04:43:27 PM PDT 24
Finished Jul 18 04:57:43 PM PDT 24
Peak memory 191976 kb
Host smart-0c70ac7e-601b-482d-846b-8b02b90f2380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239094967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.239094967
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.145718354
Short name T341
Test name
Test status
Simulation time 172530613757 ps
CPU time 460.3 seconds
Started Jul 18 04:43:24 PM PDT 24
Finished Jul 18 04:51:07 PM PDT 24
Peak memory 191664 kb
Host smart-007d3ebc-a29c-46b0-ab3d-620a007410d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145718354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.145718354
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.361147843
Short name T57
Test name
Test status
Simulation time 209312448057 ps
CPU time 404.98 seconds
Started Jul 18 04:43:28 PM PDT 24
Finished Jul 18 04:50:16 PM PDT 24
Peak memory 191968 kb
Host smart-e575d83b-5117-4368-9ea5-60c3bbd69499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361147843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.361147843
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.394784883
Short name T321
Test name
Test status
Simulation time 121226350141 ps
CPU time 118.19 seconds
Started Jul 18 04:43:31 PM PDT 24
Finished Jul 18 04:45:32 PM PDT 24
Peak memory 191568 kb
Host smart-219749fb-8245-4cd6-8840-0dc89bb0b0d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394784883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.394784883
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1380470157
Short name T117
Test name
Test status
Simulation time 21553646600 ps
CPU time 32.6 seconds
Started Jul 18 04:43:42 PM PDT 24
Finished Jul 18 04:44:16 PM PDT 24
Peak memory 191552 kb
Host smart-819bb30d-fb26-4108-9fcb-b7edc7c036b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380470157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1380470157
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.221198709
Short name T430
Test name
Test status
Simulation time 44904244159 ps
CPU time 58.98 seconds
Started Jul 18 04:42:36 PM PDT 24
Finished Jul 18 04:43:36 PM PDT 24
Peak memory 183344 kb
Host smart-3f2a180d-30e3-4700-950b-560a52c1ecac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221198709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.221198709
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1802414105
Short name T435
Test name
Test status
Simulation time 384642376 ps
CPU time 0.83 seconds
Started Jul 18 04:43:48 PM PDT 24
Finished Jul 18 04:43:51 PM PDT 24
Peak memory 183128 kb
Host smart-b17965e3-555d-4ab6-aa6f-1c51c9d91c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802414105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1802414105
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.637050047
Short name T135
Test name
Test status
Simulation time 895560088262 ps
CPU time 599.95 seconds
Started Jul 18 04:43:36 PM PDT 24
Finished Jul 18 04:53:39 PM PDT 24
Peak memory 191664 kb
Host smart-e3030067-0cf2-4d0b-8cde-03b4d2a5594e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637050047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.637050047
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3689841522
Short name T115
Test name
Test status
Simulation time 151326881232 ps
CPU time 585.08 seconds
Started Jul 18 04:43:35 PM PDT 24
Finished Jul 18 04:53:23 PM PDT 24
Peak memory 191560 kb
Host smart-596ee690-111b-423a-b102-abf62c4aa9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689841522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3689841522
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.645995681
Short name T198
Test name
Test status
Simulation time 96576849580 ps
CPU time 259.4 seconds
Started Jul 18 04:43:32 PM PDT 24
Finished Jul 18 04:47:55 PM PDT 24
Peak memory 191592 kb
Host smart-825f1478-8ab5-4f84-b217-7428b42bddab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645995681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.645995681
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.556167772
Short name T423
Test name
Test status
Simulation time 412123633972 ps
CPU time 178.05 seconds
Started Jul 18 04:43:38 PM PDT 24
Finished Jul 18 04:46:38 PM PDT 24
Peak memory 191560 kb
Host smart-041025bc-6bf6-4dbe-b973-6fb5f9882c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556167772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.556167772
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3934711048
Short name T239
Test name
Test status
Simulation time 252606384288 ps
CPU time 326.4 seconds
Started Jul 18 04:43:36 PM PDT 24
Finished Jul 18 04:49:06 PM PDT 24
Peak memory 191292 kb
Host smart-87fc5a0c-2c2a-4a57-b6fd-28e8beeb0d8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934711048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3934711048
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.829256365
Short name T445
Test name
Test status
Simulation time 438060608497 ps
CPU time 128.91 seconds
Started Jul 18 04:43:31 PM PDT 24
Finished Jul 18 04:45:43 PM PDT 24
Peak memory 191568 kb
Host smart-93e69325-116d-4118-93e7-a0786fbf0cce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829256365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.829256365
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3286096115
Short name T278
Test name
Test status
Simulation time 62935158434 ps
CPU time 108.6 seconds
Started Jul 18 04:43:46 PM PDT 24
Finished Jul 18 04:45:36 PM PDT 24
Peak memory 183096 kb
Host smart-7dc5eadc-0409-4c8e-b082-9eca70109644
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286096115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3286096115
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.722302337
Short name T123
Test name
Test status
Simulation time 84810499603 ps
CPU time 154.95 seconds
Started Jul 18 04:44:44 PM PDT 24
Finished Jul 18 04:47:20 PM PDT 24
Peak memory 191296 kb
Host smart-fe214dbc-da40-44de-949d-cfe75f35b6da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722302337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.722302337
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2927065592
Short name T449
Test name
Test status
Simulation time 322552001093 ps
CPU time 277.84 seconds
Started Jul 18 04:42:25 PM PDT 24
Finished Jul 18 04:47:05 PM PDT 24
Peak memory 183684 kb
Host smart-cbf879d8-c658-4f61-a8da-f59a970cca8b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927065592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2927065592
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1546425415
Short name T426
Test name
Test status
Simulation time 115919039594 ps
CPU time 168.85 seconds
Started Jul 18 04:42:27 PM PDT 24
Finished Jul 18 04:45:19 PM PDT 24
Peak memory 183368 kb
Host smart-20f07e76-6de4-400f-b4b5-2f50d35d8238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546425415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1546425415
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.4152491936
Short name T27
Test name
Test status
Simulation time 842601895796 ps
CPU time 1070.07 seconds
Started Jul 18 04:42:25 PM PDT 24
Finished Jul 18 05:00:17 PM PDT 24
Peak memory 191552 kb
Host smart-38d053d3-2a09-4e50-9b1a-8f7c46aab90e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152491936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.4152491936
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2077842125
Short name T410
Test name
Test status
Simulation time 774638476551 ps
CPU time 261.92 seconds
Started Jul 18 04:42:32 PM PDT 24
Finished Jul 18 04:46:55 PM PDT 24
Peak memory 191552 kb
Host smart-56bc1c0d-2acb-49fb-8540-17c9f629419f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077842125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2077842125
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.3162897338
Short name T6
Test name
Test status
Simulation time 43484928735 ps
CPU time 68.13 seconds
Started Jul 18 04:43:32 PM PDT 24
Finished Jul 18 04:44:43 PM PDT 24
Peak memory 183348 kb
Host smart-e4044fe1-4cf8-4516-9faf-db0b49ea47ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162897338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3162897338
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2480426538
Short name T282
Test name
Test status
Simulation time 216655457713 ps
CPU time 147.16 seconds
Started Jul 18 04:43:33 PM PDT 24
Finished Jul 18 04:46:03 PM PDT 24
Peak memory 191568 kb
Host smart-2224d5b4-0c37-43a7-a43a-5528736b4e2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480426538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2480426538
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1286252124
Short name T333
Test name
Test status
Simulation time 64887769589 ps
CPU time 376.43 seconds
Started Jul 18 04:43:32 PM PDT 24
Finished Jul 18 04:49:52 PM PDT 24
Peak memory 183240 kb
Host smart-e73b8ea5-8f3f-4533-afaa-97f04f7a02be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286252124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1286252124
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.449548759
Short name T208
Test name
Test status
Simulation time 393252835672 ps
CPU time 431.27 seconds
Started Jul 18 04:43:46 PM PDT 24
Finished Jul 18 04:50:58 PM PDT 24
Peak memory 191556 kb
Host smart-43292c9c-a740-4d90-a43e-0d35bd8b41ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449548759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.449548759
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3694699162
Short name T262
Test name
Test status
Simulation time 74281100213 ps
CPU time 148.62 seconds
Started Jul 18 04:43:34 PM PDT 24
Finished Jul 18 04:46:06 PM PDT 24
Peak memory 191604 kb
Host smart-1b6711f1-2c82-4232-b305-bfe13a645b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694699162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3694699162
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2791354110
Short name T295
Test name
Test status
Simulation time 23851760697 ps
CPU time 194.46 seconds
Started Jul 18 04:43:40 PM PDT 24
Finished Jul 18 04:46:56 PM PDT 24
Peak memory 183360 kb
Host smart-7c120d71-0b02-4d6b-bcec-e3887b52922c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791354110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2791354110
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2219590582
Short name T196
Test name
Test status
Simulation time 246318929852 ps
CPU time 149.56 seconds
Started Jul 18 04:42:39 PM PDT 24
Finished Jul 18 04:45:11 PM PDT 24
Peak memory 183336 kb
Host smart-d4c7d235-6b16-4208-8b9e-275740ba09fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219590582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2219590582
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3304043504
Short name T375
Test name
Test status
Simulation time 27728237619 ps
CPU time 12.69 seconds
Started Jul 18 04:42:44 PM PDT 24
Finished Jul 18 04:42:59 PM PDT 24
Peak memory 183340 kb
Host smart-5988e68b-9dbd-43a7-80cb-7b48de356f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304043504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3304043504
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.372082435
Short name T315
Test name
Test status
Simulation time 645806302 ps
CPU time 1.32 seconds
Started Jul 18 04:42:46 PM PDT 24
Finished Jul 18 04:42:50 PM PDT 24
Peak memory 194520 kb
Host smart-3ec3d551-899d-4b9f-87de-06450b1bca96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372082435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.372082435
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.932715682
Short name T13
Test name
Test status
Simulation time 431011893182 ps
CPU time 513.94 seconds
Started Jul 18 04:42:42 PM PDT 24
Finished Jul 18 04:51:18 PM PDT 24
Peak memory 212676 kb
Host smart-e852ebd3-754b-40e0-a07d-af28c3cb0686
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932715682 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.932715682
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.2130260113
Short name T311
Test name
Test status
Simulation time 159303630412 ps
CPU time 619.69 seconds
Started Jul 18 04:43:45 PM PDT 24
Finished Jul 18 04:54:05 PM PDT 24
Peak memory 183352 kb
Host smart-2c54df72-3495-4a1a-916c-b05e10e30335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130260113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2130260113
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1582773593
Short name T175
Test name
Test status
Simulation time 108457109496 ps
CPU time 385.05 seconds
Started Jul 18 04:43:38 PM PDT 24
Finished Jul 18 04:50:05 PM PDT 24
Peak memory 191532 kb
Host smart-1b00618b-539a-4314-8a77-4c399d09c3a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582773593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1582773593
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1759291257
Short name T221
Test name
Test status
Simulation time 88750132508 ps
CPU time 139.5 seconds
Started Jul 18 04:43:36 PM PDT 24
Finished Jul 18 04:45:58 PM PDT 24
Peak memory 183356 kb
Host smart-b50874f9-1ffd-42a6-82ac-7503e86b1dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759291257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1759291257
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.4115596562
Short name T191
Test name
Test status
Simulation time 182577864428 ps
CPU time 550.05 seconds
Started Jul 18 04:43:39 PM PDT 24
Finished Jul 18 04:52:51 PM PDT 24
Peak memory 191548 kb
Host smart-ae122725-82e9-4a8f-bf5e-043232c70701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115596562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.4115596562
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2937349979
Short name T184
Test name
Test status
Simulation time 359657307965 ps
CPU time 282.97 seconds
Started Jul 18 04:43:33 PM PDT 24
Finished Jul 18 04:48:19 PM PDT 24
Peak memory 191604 kb
Host smart-09f31065-7c85-407f-afbd-78c1aed0256b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937349979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2937349979
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.360906612
Short name T141
Test name
Test status
Simulation time 25651205999 ps
CPU time 39.63 seconds
Started Jul 18 04:43:35 PM PDT 24
Finished Jul 18 04:44:17 PM PDT 24
Peak memory 183384 kb
Host smart-b1396a8b-86a1-487c-b566-d2e0a7e1122c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360906612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.360906612
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1178970649
Short name T19
Test name
Test status
Simulation time 344075666037 ps
CPU time 573.24 seconds
Started Jul 18 04:42:54 PM PDT 24
Finished Jul 18 04:52:29 PM PDT 24
Peak memory 183344 kb
Host smart-9ec49a76-225b-4584-97de-75878b25eeab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178970649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1178970649
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3018987945
Short name T357
Test name
Test status
Simulation time 50744706219 ps
CPU time 76.94 seconds
Started Jul 18 04:42:52 PM PDT 24
Finished Jul 18 04:44:12 PM PDT 24
Peak memory 183396 kb
Host smart-92fc834d-3947-466d-96b1-356462181b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018987945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3018987945
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.958295200
Short name T220
Test name
Test status
Simulation time 151422683773 ps
CPU time 313.52 seconds
Started Jul 18 04:42:43 PM PDT 24
Finished Jul 18 04:47:58 PM PDT 24
Peak memory 183368 kb
Host smart-ba3f95d7-cf77-4b38-8471-4b096c106664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958295200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.958295200
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.3238837731
Short name T36
Test name
Test status
Simulation time 74274645650 ps
CPU time 269.47 seconds
Started Jul 18 04:42:39 PM PDT 24
Finished Jul 18 04:47:11 PM PDT 24
Peak memory 206324 kb
Host smart-6e93b79b-c518-47ae-8748-f085b2bd458b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238837731 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.3238837731
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/173.rv_timer_random.3522560706
Short name T129
Test name
Test status
Simulation time 140604007440 ps
CPU time 230.7 seconds
Started Jul 18 04:43:39 PM PDT 24
Finished Jul 18 04:47:31 PM PDT 24
Peak memory 191548 kb
Host smart-c96f79c3-4ef5-4881-be9a-178bc3a204a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522560706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3522560706
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3884464352
Short name T246
Test name
Test status
Simulation time 274563984849 ps
CPU time 332.71 seconds
Started Jul 18 04:43:41 PM PDT 24
Finished Jul 18 04:49:15 PM PDT 24
Peak memory 191548 kb
Host smart-661ffe55-1904-4a71-badf-284c2dfd7f2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884464352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3884464352
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.4290780668
Short name T157
Test name
Test status
Simulation time 137168222509 ps
CPU time 581.08 seconds
Started Jul 18 04:43:35 PM PDT 24
Finished Jul 18 04:53:19 PM PDT 24
Peak memory 191556 kb
Host smart-8dc534e1-e58f-41fd-8561-b05474ac8098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290780668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.4290780668
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3006914337
Short name T177
Test name
Test status
Simulation time 120869032712 ps
CPU time 328.44 seconds
Started Jul 18 04:43:36 PM PDT 24
Finished Jul 18 04:49:08 PM PDT 24
Peak memory 191560 kb
Host smart-c02b510d-b6f9-4b70-b450-53c83318a52f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006914337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3006914337
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2536010928
Short name T352
Test name
Test status
Simulation time 103314962895 ps
CPU time 185.41 seconds
Started Jul 18 04:43:34 PM PDT 24
Finished Jul 18 04:46:43 PM PDT 24
Peak memory 191568 kb
Host smart-e2a255aa-e4d7-4089-b7ab-831ec04ef8dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536010928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2536010928
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.497334225
Short name T148
Test name
Test status
Simulation time 134398849364 ps
CPU time 700.52 seconds
Started Jul 18 04:43:36 PM PDT 24
Finished Jul 18 04:55:19 PM PDT 24
Peak memory 191556 kb
Host smart-1cbdc730-fda5-424b-afdc-a39aed3ded05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497334225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.497334225
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3010881714
Short name T266
Test name
Test status
Simulation time 324890869280 ps
CPU time 1070.82 seconds
Started Jul 18 04:43:41 PM PDT 24
Finished Jul 18 05:01:32 PM PDT 24
Peak memory 191580 kb
Host smart-9b29417c-e3f3-42e1-aadf-5f62f01d135c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010881714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3010881714
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.507641660
Short name T347
Test name
Test status
Simulation time 6511596293 ps
CPU time 11.91 seconds
Started Jul 18 04:42:47 PM PDT 24
Finished Jul 18 04:43:02 PM PDT 24
Peak memory 183360 kb
Host smart-7f088062-7c47-4fe9-af25-15ab8d04ee44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507641660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.507641660
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1389102490
Short name T413
Test name
Test status
Simulation time 450288654137 ps
CPU time 121.41 seconds
Started Jul 18 04:42:41 PM PDT 24
Finished Jul 18 04:44:45 PM PDT 24
Peak memory 183308 kb
Host smart-f3ddca86-fe31-45e1-8b0f-6e908b76ca9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389102490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1389102490
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.3257216253
Short name T436
Test name
Test status
Simulation time 1910208414 ps
CPU time 3.7 seconds
Started Jul 18 04:42:50 PM PDT 24
Finished Jul 18 04:43:00 PM PDT 24
Peak memory 183120 kb
Host smart-b142b1ba-2992-4bd7-9ada-6c9d4a42531e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257216253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3257216253
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3100049885
Short name T215
Test name
Test status
Simulation time 150540454236 ps
CPU time 126.25 seconds
Started Jul 18 04:42:44 PM PDT 24
Finished Jul 18 04:44:52 PM PDT 24
Peak memory 191532 kb
Host smart-eb9c1143-100a-49c6-a887-0cde11004103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100049885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3100049885
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.3449968929
Short name T186
Test name
Test status
Simulation time 333758842210 ps
CPU time 894.92 seconds
Started Jul 18 04:43:45 PM PDT 24
Finished Jul 18 04:58:42 PM PDT 24
Peak memory 191292 kb
Host smart-fa07bf80-c674-4157-a133-1b08ad5a613b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449968929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3449968929
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3590614407
Short name T280
Test name
Test status
Simulation time 295558170803 ps
CPU time 546.08 seconds
Started Jul 18 04:43:38 PM PDT 24
Finished Jul 18 04:52:46 PM PDT 24
Peak memory 191560 kb
Host smart-4f7c3c8c-769b-4c70-af8c-46b3f8e22aca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590614407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3590614407
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1567818839
Short name T274
Test name
Test status
Simulation time 17589555625 ps
CPU time 58.34 seconds
Started Jul 18 04:44:36 PM PDT 24
Finished Jul 18 04:45:36 PM PDT 24
Peak memory 182576 kb
Host smart-8b3b3b91-0bd4-4da0-a50a-8799b17b83e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567818839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1567818839
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3628436315
Short name T10
Test name
Test status
Simulation time 145350236571 ps
CPU time 108.23 seconds
Started Jul 18 04:43:44 PM PDT 24
Finished Jul 18 04:45:33 PM PDT 24
Peak memory 183388 kb
Host smart-3768e9cf-657f-4c6f-a818-596f263c4605
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628436315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3628436315
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3467739403
Short name T203
Test name
Test status
Simulation time 620010738456 ps
CPU time 951.39 seconds
Started Jul 18 04:43:32 PM PDT 24
Finished Jul 18 04:59:27 PM PDT 24
Peak memory 191556 kb
Host smart-9b87c854-9dea-47b1-b99d-b54e1d8f7ecd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467739403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3467739403
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3393578133
Short name T351
Test name
Test status
Simulation time 25577958469 ps
CPU time 42.43 seconds
Started Jul 18 04:43:40 PM PDT 24
Finished Jul 18 04:44:24 PM PDT 24
Peak memory 183356 kb
Host smart-79e87e34-7521-4524-a959-1cbf85a116dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393578133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3393578133
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2884847898
Short name T329
Test name
Test status
Simulation time 176381703684 ps
CPU time 896.55 seconds
Started Jul 18 04:43:45 PM PDT 24
Finished Jul 18 04:58:43 PM PDT 24
Peak memory 191568 kb
Host smart-5bf72b74-e31f-45a6-aea1-e3adcabe56b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884847898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2884847898
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2112479745
Short name T334
Test name
Test status
Simulation time 73213183319 ps
CPU time 387.74 seconds
Started Jul 18 04:43:49 PM PDT 24
Finished Jul 18 04:50:19 PM PDT 24
Peak memory 191560 kb
Host smart-1189bbbe-9c67-4707-bed8-dd54d3a475b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112479745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2112479745
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.930494443
Short name T285
Test name
Test status
Simulation time 99192692782 ps
CPU time 164.94 seconds
Started Jul 18 04:42:48 PM PDT 24
Finished Jul 18 04:45:36 PM PDT 24
Peak memory 183364 kb
Host smart-ee2cc7d0-310d-48d4-a965-97b4b6f426e2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930494443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.930494443
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.8118206
Short name T443
Test name
Test status
Simulation time 730173586009 ps
CPU time 161.52 seconds
Started Jul 18 04:42:47 PM PDT 24
Finished Jul 18 04:45:32 PM PDT 24
Peak memory 183344 kb
Host smart-6add91e8-f448-4196-9273-14a149b519c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8118206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.8118206
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2349003939
Short name T143
Test name
Test status
Simulation time 190126227048 ps
CPU time 579.08 seconds
Started Jul 18 04:42:48 PM PDT 24
Finished Jul 18 04:52:31 PM PDT 24
Peak memory 191572 kb
Host smart-d8c67e0d-d1d0-420b-8e91-910318229ee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349003939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2349003939
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.283329524
Short name T412
Test name
Test status
Simulation time 765811639 ps
CPU time 1.86 seconds
Started Jul 18 04:42:48 PM PDT 24
Finished Jul 18 04:42:53 PM PDT 24
Peak memory 191544 kb
Host smart-0360b773-2ae3-4fb3-bf10-9aecce06a559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283329524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.283329524
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.350773591
Short name T195
Test name
Test status
Simulation time 378076450088 ps
CPU time 317.24 seconds
Started Jul 18 04:42:41 PM PDT 24
Finished Jul 18 04:48:01 PM PDT 24
Peak memory 191564 kb
Host smart-9c042929-b229-4f25-ae97-758edab46275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350773591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
350773591
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.480626600
Short name T269
Test name
Test status
Simulation time 280385982314 ps
CPU time 1500.66 seconds
Started Jul 18 04:43:46 PM PDT 24
Finished Jul 18 05:08:49 PM PDT 24
Peak memory 191548 kb
Host smart-6b82c410-1f85-4500-b67a-71529c4f21fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480626600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.480626600
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.565600768
Short name T205
Test name
Test status
Simulation time 214550912403 ps
CPU time 136.69 seconds
Started Jul 18 04:43:47 PM PDT 24
Finished Jul 18 04:46:06 PM PDT 24
Peak memory 191564 kb
Host smart-db6fa027-0caa-439a-81e4-3921eca67c60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565600768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.565600768
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3866541688
Short name T132
Test name
Test status
Simulation time 107181671738 ps
CPU time 72.82 seconds
Started Jul 18 04:43:45 PM PDT 24
Finished Jul 18 04:44:59 PM PDT 24
Peak memory 191664 kb
Host smart-c98683e5-11ae-4ea4-809a-93d0ee08149a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866541688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3866541688
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2866194438
Short name T343
Test name
Test status
Simulation time 666244500713 ps
CPU time 243.39 seconds
Started Jul 18 04:43:47 PM PDT 24
Finished Jul 18 04:47:53 PM PDT 24
Peak memory 191596 kb
Host smart-96e17b8d-e2ec-4875-a0ef-f44a3135746a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866194438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2866194438
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.4155368407
Short name T305
Test name
Test status
Simulation time 125104474811 ps
CPU time 122.98 seconds
Started Jul 18 04:43:44 PM PDT 24
Finished Jul 18 04:45:47 PM PDT 24
Peak memory 191568 kb
Host smart-9b93da7a-f8ae-42f7-9c2d-fb2d914e0f4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155368407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.4155368407
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1062910607
Short name T237
Test name
Test status
Simulation time 48248856147 ps
CPU time 162.89 seconds
Started Jul 18 04:43:48 PM PDT 24
Finished Jul 18 04:46:33 PM PDT 24
Peak memory 191952 kb
Host smart-3954ae4d-a0aa-4984-9a6d-e51b1c2abfab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062910607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1062910607
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2520167855
Short name T328
Test name
Test status
Simulation time 33650952327 ps
CPU time 106.96 seconds
Started Jul 18 04:43:48 PM PDT 24
Finished Jul 18 04:45:38 PM PDT 24
Peak memory 191548 kb
Host smart-7bcf7603-95d4-46bc-97a1-685db8e1b051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520167855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2520167855
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.5143975
Short name T55
Test name
Test status
Simulation time 45460281608 ps
CPU time 41.27 seconds
Started Jul 18 04:43:44 PM PDT 24
Finished Jul 18 04:44:26 PM PDT 24
Peak memory 183356 kb
Host smart-c74090b8-37eb-4895-be68-bd54a1d7c7da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5143975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.5143975
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3852745153
Short name T111
Test name
Test status
Simulation time 198520671473 ps
CPU time 302.24 seconds
Started Jul 18 04:42:29 PM PDT 24
Finished Jul 18 04:47:33 PM PDT 24
Peak memory 183352 kb
Host smart-7593f3d6-50b4-4cdc-9e03-51ac5f209612
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852745153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3852745153
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2800643212
Short name T391
Test name
Test status
Simulation time 252768894155 ps
CPU time 92.61 seconds
Started Jul 18 04:42:29 PM PDT 24
Finished Jul 18 04:44:04 PM PDT 24
Peak memory 183356 kb
Host smart-5ece9839-49e5-4658-b1a7-5116c683c774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800643212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2800643212
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1935025164
Short name T264
Test name
Test status
Simulation time 898776347879 ps
CPU time 792.8 seconds
Started Jul 18 04:42:20 PM PDT 24
Finished Jul 18 04:55:35 PM PDT 24
Peak memory 195168 kb
Host smart-0a1a90f7-0cd9-42c1-8670-4a0e0c083a8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935025164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1935025164
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2187809561
Short name T332
Test name
Test status
Simulation time 8911871705 ps
CPU time 15.38 seconds
Started Jul 18 04:42:34 PM PDT 24
Finished Jul 18 04:42:50 PM PDT 24
Peak memory 183400 kb
Host smart-82cfebd5-cf2f-42ba-b193-e915f0c33728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187809561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2187809561
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3789350617
Short name T319
Test name
Test status
Simulation time 52178043447 ps
CPU time 35.59 seconds
Started Jul 18 04:42:41 PM PDT 24
Finished Jul 18 04:43:19 PM PDT 24
Peak memory 183256 kb
Host smart-f145c437-d6a4-4277-98a5-a04d199dd4cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789350617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3789350617
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.4057386261
Short name T364
Test name
Test status
Simulation time 114319822197 ps
CPU time 85.52 seconds
Started Jul 18 04:42:44 PM PDT 24
Finished Jul 18 04:44:11 PM PDT 24
Peak memory 183364 kb
Host smart-fc4a0046-f465-48f7-80ad-1c5c558b4dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057386261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.4057386261
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2322487921
Short name T204
Test name
Test status
Simulation time 259093879305 ps
CPU time 566.66 seconds
Started Jul 18 04:42:47 PM PDT 24
Finished Jul 18 04:52:17 PM PDT 24
Peak memory 191572 kb
Host smart-99421936-7953-4228-8daa-9bc4091ed5b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322487921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2322487921
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3772123949
Short name T446
Test name
Test status
Simulation time 177842328423 ps
CPU time 93.37 seconds
Started Jul 18 04:42:44 PM PDT 24
Finished Jul 18 04:44:19 PM PDT 24
Peak memory 191604 kb
Host smart-290fc56a-7011-4f71-9d8d-b9b5e693f049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772123949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3772123949
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1116990259
Short name T353
Test name
Test status
Simulation time 1065521507230 ps
CPU time 691.53 seconds
Started Jul 18 04:42:43 PM PDT 24
Finished Jul 18 04:54:17 PM PDT 24
Peak memory 191548 kb
Host smart-7b92a9c1-2954-4b10-bd71-f166fd270b94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116990259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1116990259
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1542603460
Short name T113
Test name
Test status
Simulation time 1168718123766 ps
CPU time 660.93 seconds
Started Jul 18 04:42:46 PM PDT 24
Finished Jul 18 04:53:49 PM PDT 24
Peak memory 183392 kb
Host smart-784635da-e5a2-4ca5-a779-df795739b0c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542603460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1542603460
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3185535559
Short name T397
Test name
Test status
Simulation time 110087097723 ps
CPU time 168.97 seconds
Started Jul 18 04:42:56 PM PDT 24
Finished Jul 18 04:45:46 PM PDT 24
Peak memory 183364 kb
Host smart-57bab5fc-4355-4b8f-98da-3a594dea3987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185535559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3185535559
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2712390133
Short name T448
Test name
Test status
Simulation time 536859448434 ps
CPU time 591.04 seconds
Started Jul 18 04:42:49 PM PDT 24
Finished Jul 18 04:52:43 PM PDT 24
Peak memory 191600 kb
Host smart-76177678-9ad0-45bb-816a-947539ca82dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712390133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2712390133
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.4045666806
Short name T395
Test name
Test status
Simulation time 12415105521 ps
CPU time 86.7 seconds
Started Jul 18 04:42:54 PM PDT 24
Finished Jul 18 04:44:22 PM PDT 24
Peak memory 191560 kb
Host smart-b3ac256b-ca7c-492b-a8db-2593b1c5f13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045666806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.4045666806
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.546217911
Short name T385
Test name
Test status
Simulation time 374669484254 ps
CPU time 162.92 seconds
Started Jul 18 04:42:50 PM PDT 24
Finished Jul 18 04:45:35 PM PDT 24
Peak memory 183360 kb
Host smart-f78f0266-8d41-448e-815e-7f63461db1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546217911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.546217911
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1288568097
Short name T378
Test name
Test status
Simulation time 751436731 ps
CPU time 1 seconds
Started Jul 18 04:43:01 PM PDT 24
Finished Jul 18 04:43:03 PM PDT 24
Peak memory 193072 kb
Host smart-35b1e996-4400-47ac-9827-4d7f7edad2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288568097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1288568097
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3562081937
Short name T121
Test name
Test status
Simulation time 3057777383744 ps
CPU time 918.21 seconds
Started Jul 18 04:43:00 PM PDT 24
Finished Jul 18 04:58:19 PM PDT 24
Peak memory 191556 kb
Host smart-99dccb94-57f6-44a6-8e1a-d571c0161c25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562081937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3562081937
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.974347622
Short name T34
Test name
Test status
Simulation time 167824221999 ps
CPU time 419.29 seconds
Started Jul 18 04:42:49 PM PDT 24
Finished Jul 18 04:49:51 PM PDT 24
Peak memory 206384 kb
Host smart-91486e75-2273-4647-ad02-e3abd9d1c3e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974347622 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.974347622
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2450124676
Short name T8
Test name
Test status
Simulation time 652866771876 ps
CPU time 621.6 seconds
Started Jul 18 04:42:41 PM PDT 24
Finished Jul 18 04:53:05 PM PDT 24
Peak memory 183348 kb
Host smart-d3a56b91-7f59-4ddc-b308-5c07cc054afd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450124676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2450124676
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2414948383
Short name T366
Test name
Test status
Simulation time 751189710709 ps
CPU time 193.4 seconds
Started Jul 18 04:42:46 PM PDT 24
Finished Jul 18 04:46:02 PM PDT 24
Peak memory 183376 kb
Host smart-6f22fc37-837a-4813-ac52-594ff5a048b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414948383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2414948383
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.460495909
Short name T308
Test name
Test status
Simulation time 19925709817 ps
CPU time 33.79 seconds
Started Jul 18 04:42:46 PM PDT 24
Finished Jul 18 04:43:23 PM PDT 24
Peak memory 183360 kb
Host smart-c6a6d63c-e08c-4b0c-80ca-ce0a3cb6366c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460495909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.460495909
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2176621995
Short name T422
Test name
Test status
Simulation time 769311399 ps
CPU time 1.06 seconds
Started Jul 18 04:42:53 PM PDT 24
Finished Jul 18 04:42:56 PM PDT 24
Peak memory 193364 kb
Host smart-fd12a6fa-4b65-4852-ac36-9cc09fb61143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176621995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2176621995
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1843616885
Short name T189
Test name
Test status
Simulation time 271517465538 ps
CPU time 354.6 seconds
Started Jul 18 04:42:40 PM PDT 24
Finished Jul 18 04:48:37 PM PDT 24
Peak memory 183720 kb
Host smart-d586d697-8413-413d-8f70-74158c059c30
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843616885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1843616885
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1067804871
Short name T400
Test name
Test status
Simulation time 124507731370 ps
CPU time 195.68 seconds
Started Jul 18 04:42:47 PM PDT 24
Finished Jul 18 04:46:06 PM PDT 24
Peak memory 183468 kb
Host smart-39f2926f-51a6-43e5-9b60-eafa8e17cc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067804871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1067804871
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.4048225300
Short name T429
Test name
Test status
Simulation time 79679719716 ps
CPU time 46.63 seconds
Started Jul 18 04:42:45 PM PDT 24
Finished Jul 18 04:43:34 PM PDT 24
Peak memory 183484 kb
Host smart-07c44018-74ef-48d2-90b6-1187fb132d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048225300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.4048225300
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.3833535054
Short name T12
Test name
Test status
Simulation time 286335222643 ps
CPU time 406.1 seconds
Started Jul 18 04:42:55 PM PDT 24
Finished Jul 18 04:49:43 PM PDT 24
Peak memory 206284 kb
Host smart-143f5ca7-76f4-4c9f-bbfe-488fe71aee4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833535054 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.3833535054
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1917930027
Short name T360
Test name
Test status
Simulation time 179167599797 ps
CPU time 245.07 seconds
Started Jul 18 04:42:51 PM PDT 24
Finished Jul 18 04:46:58 PM PDT 24
Peak memory 183396 kb
Host smart-7bccf7e2-e4d9-4d85-a452-56c5ff1c55ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917930027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1917930027
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.974272673
Short name T292
Test name
Test status
Simulation time 404149254258 ps
CPU time 242.44 seconds
Started Jul 18 04:43:02 PM PDT 24
Finished Jul 18 04:47:07 PM PDT 24
Peak memory 191544 kb
Host smart-a7df78ac-afde-4fbc-a548-0d18f673efe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974272673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.974272673
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2906332894
Short name T382
Test name
Test status
Simulation time 198415608 ps
CPU time 0.82 seconds
Started Jul 18 04:43:02 PM PDT 24
Finished Jul 18 04:43:05 PM PDT 24
Peak memory 183156 kb
Host smart-e738570b-cfab-41e3-9df0-b123d102e186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906332894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2906332894
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2897981171
Short name T201
Test name
Test status
Simulation time 527642678015 ps
CPU time 914.91 seconds
Started Jul 18 04:43:00 PM PDT 24
Finished Jul 18 04:58:17 PM PDT 24
Peak memory 183352 kb
Host smart-b135633b-2380-455c-aaa5-c92e161cd882
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897981171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2897981171
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.291624707
Short name T388
Test name
Test status
Simulation time 507617040847 ps
CPU time 216.4 seconds
Started Jul 18 04:42:53 PM PDT 24
Finished Jul 18 04:46:32 PM PDT 24
Peak memory 183376 kb
Host smart-b2ce32dd-90fd-401a-833f-dba92939e6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291624707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.291624707
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3891119348
Short name T116
Test name
Test status
Simulation time 441873283217 ps
CPU time 359.35 seconds
Started Jul 18 04:43:06 PM PDT 24
Finished Jul 18 04:49:07 PM PDT 24
Peak memory 191592 kb
Host smart-67c6801d-9177-4eda-9405-5d58339d430c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891119348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3891119348
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2301224562
Short name T363
Test name
Test status
Simulation time 73558163 ps
CPU time 0.66 seconds
Started Jul 18 04:42:57 PM PDT 24
Finished Jul 18 04:42:58 PM PDT 24
Peak memory 183128 kb
Host smart-c0b96f62-476c-410d-977e-596ae17e2219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301224562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2301224562
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.418672052
Short name T126
Test name
Test status
Simulation time 513488612927 ps
CPU time 481.32 seconds
Started Jul 18 04:43:01 PM PDT 24
Finished Jul 18 04:51:04 PM PDT 24
Peak memory 183364 kb
Host smart-446c1838-38b8-4177-a58f-cc906139fb63
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418672052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.418672052
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.707960440
Short name T361
Test name
Test status
Simulation time 623121297257 ps
CPU time 174.17 seconds
Started Jul 18 04:42:54 PM PDT 24
Finished Jul 18 04:45:51 PM PDT 24
Peak memory 183376 kb
Host smart-d2d81b4f-5a0d-4fce-b889-a6841589743f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707960440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.707960440
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.498038578
Short name T42
Test name
Test status
Simulation time 137917791910 ps
CPU time 605.67 seconds
Started Jul 18 04:42:59 PM PDT 24
Finished Jul 18 04:53:06 PM PDT 24
Peak memory 191564 kb
Host smart-0c663f5a-bd57-4ce7-ac3d-71b21d1ef08b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498038578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.498038578
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2178565200
Short name T5
Test name
Test status
Simulation time 154437848424 ps
CPU time 221.46 seconds
Started Jul 18 04:42:52 PM PDT 24
Finished Jul 18 04:46:36 PM PDT 24
Peak memory 183364 kb
Host smart-08bfae97-2361-4155-9526-31b46f3dec4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178565200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2178565200
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2793152882
Short name T433
Test name
Test status
Simulation time 34951800612 ps
CPU time 20.57 seconds
Started Jul 18 04:43:06 PM PDT 24
Finished Jul 18 04:43:28 PM PDT 24
Peak memory 183456 kb
Host smart-35adab9f-9ef5-4a72-b827-5f6063c89c49
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793152882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2793152882
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3568741981
Short name T434
Test name
Test status
Simulation time 26666672238 ps
CPU time 39.07 seconds
Started Jul 18 04:43:02 PM PDT 24
Finished Jul 18 04:43:43 PM PDT 24
Peak memory 183340 kb
Host smart-e5745649-c930-4ce2-a8cd-f5358d170058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568741981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3568741981
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2530473662
Short name T419
Test name
Test status
Simulation time 176411817355 ps
CPU time 123.95 seconds
Started Jul 18 04:43:00 PM PDT 24
Finished Jul 18 04:45:05 PM PDT 24
Peak memory 194632 kb
Host smart-eef5a17a-3a35-4061-af84-20f16107b8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530473662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2530473662
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.186922463
Short name T174
Test name
Test status
Simulation time 456456034666 ps
CPU time 327.26 seconds
Started Jul 18 04:42:40 PM PDT 24
Finished Jul 18 04:48:10 PM PDT 24
Peak memory 191548 kb
Host smart-e36fc549-d658-4401-8183-737718b77760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186922463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
186922463
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1536762551
Short name T401
Test name
Test status
Simulation time 80747761822 ps
CPU time 41.74 seconds
Started Jul 18 04:43:17 PM PDT 24
Finished Jul 18 04:44:00 PM PDT 24
Peak memory 183352 kb
Host smart-4b8bc3d0-549b-41d4-b46f-ec737f2cdbba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536762551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1536762551
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.835319620
Short name T368
Test name
Test status
Simulation time 301322408176 ps
CPU time 254.35 seconds
Started Jul 18 04:43:12 PM PDT 24
Finished Jul 18 04:47:29 PM PDT 24
Peak memory 183376 kb
Host smart-10f06a3a-af54-4fab-91ea-26dedf25158b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835319620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.835319620
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2880443300
Short name T342
Test name
Test status
Simulation time 53852927408 ps
CPU time 226.77 seconds
Started Jul 18 04:43:18 PM PDT 24
Finished Jul 18 04:47:07 PM PDT 24
Peak memory 191620 kb
Host smart-1e88c145-4532-4a08-8d0e-5ced07620055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880443300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2880443300
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.587852063
Short name T35
Test name
Test status
Simulation time 39334405781 ps
CPU time 159.36 seconds
Started Jul 18 04:43:07 PM PDT 24
Finished Jul 18 04:45:48 PM PDT 24
Peak memory 198052 kb
Host smart-e0b0b05d-644c-4e61-b27e-7707deb16099
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587852063 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.587852063
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.545879718
Short name T336
Test name
Test status
Simulation time 732038207371 ps
CPU time 453.79 seconds
Started Jul 18 04:42:25 PM PDT 24
Finished Jul 18 04:50:01 PM PDT 24
Peak memory 183360 kb
Host smart-b5dbf1e9-6cde-4032-a29d-202b24bd69db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545879718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.545879718
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3558510192
Short name T358
Test name
Test status
Simulation time 576293443780 ps
CPU time 234.01 seconds
Started Jul 18 04:42:34 PM PDT 24
Finished Jul 18 04:46:29 PM PDT 24
Peak memory 183364 kb
Host smart-fc39d1f6-5e8a-490b-bfec-0012fd5182b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558510192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3558510192
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.2454179157
Short name T97
Test name
Test status
Simulation time 26934309510 ps
CPU time 44.91 seconds
Started Jul 18 04:42:30 PM PDT 24
Finished Jul 18 04:43:17 PM PDT 24
Peak memory 183356 kb
Host smart-7254bb53-8650-4d7d-ba30-bbef413f4a5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454179157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2454179157
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1459631530
Short name T367
Test name
Test status
Simulation time 29859205200 ps
CPU time 74.99 seconds
Started Jul 18 04:42:39 PM PDT 24
Finished Jul 18 04:43:57 PM PDT 24
Peak memory 191544 kb
Host smart-ae1b66e8-0cca-4343-a34e-d50962a3f27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459631530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1459631530
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2730218163
Short name T17
Test name
Test status
Simulation time 388485480 ps
CPU time 0.96 seconds
Started Jul 18 04:42:24 PM PDT 24
Finished Jul 18 04:42:27 PM PDT 24
Peak memory 216120 kb
Host smart-fb49a596-1d0f-480f-a98a-adfdb24c1b8b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730218163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2730218163
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3315924191
Short name T346
Test name
Test status
Simulation time 10103739012 ps
CPU time 17.7 seconds
Started Jul 18 04:43:01 PM PDT 24
Finished Jul 18 04:43:20 PM PDT 24
Peak memory 183364 kb
Host smart-d47d5680-3bc5-40b9-a82e-d08ed39b69c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315924191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3315924191
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3105030474
Short name T365
Test name
Test status
Simulation time 97719987955 ps
CPU time 125.73 seconds
Started Jul 18 04:43:11 PM PDT 24
Finished Jul 18 04:45:19 PM PDT 24
Peak memory 183392 kb
Host smart-ec395d17-35c0-4b78-bf2e-d856d80ff94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105030474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3105030474
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1855219094
Short name T180
Test name
Test status
Simulation time 340702605139 ps
CPU time 348.5 seconds
Started Jul 18 04:43:04 PM PDT 24
Finished Jul 18 04:48:54 PM PDT 24
Peak memory 191568 kb
Host smart-4c199db0-59bc-4e47-b984-1eff0091ae06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855219094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1855219094
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3344227800
Short name T384
Test name
Test status
Simulation time 3978267764 ps
CPU time 6.82 seconds
Started Jul 18 04:43:15 PM PDT 24
Finished Jul 18 04:43:24 PM PDT 24
Peak memory 183344 kb
Host smart-54bfba8c-bce2-4db9-89b4-004625b9aad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344227800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3344227800
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1081263532
Short name T61
Test name
Test status
Simulation time 1796997096229 ps
CPU time 914.79 seconds
Started Jul 18 04:43:11 PM PDT 24
Finished Jul 18 04:58:28 PM PDT 24
Peak memory 194692 kb
Host smart-243c9f42-1db8-487d-aabe-f01920a41841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081263532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1081263532
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.4251095084
Short name T40
Test name
Test status
Simulation time 28891113227 ps
CPU time 295.59 seconds
Started Jul 18 04:43:15 PM PDT 24
Finished Jul 18 04:48:12 PM PDT 24
Peak memory 198080 kb
Host smart-0486f637-25d7-4a0a-8ec6-8beed53b5892
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251095084 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.4251095084
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3442155456
Short name T22
Test name
Test status
Simulation time 1277032920028 ps
CPU time 1091.67 seconds
Started Jul 18 04:43:05 PM PDT 24
Finished Jul 18 05:01:18 PM PDT 24
Peak memory 183336 kb
Host smart-1667a640-ffd0-4f78-96a4-6e11e5f8a33e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442155456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3442155456
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1609301166
Short name T392
Test name
Test status
Simulation time 400793082394 ps
CPU time 157.76 seconds
Started Jul 18 04:43:05 PM PDT 24
Finished Jul 18 04:45:44 PM PDT 24
Peak memory 183348 kb
Host smart-84057707-5909-4371-b2d6-0968d5d1ed9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609301166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1609301166
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3342425197
Short name T216
Test name
Test status
Simulation time 41590666160 ps
CPU time 62.66 seconds
Started Jul 18 04:43:12 PM PDT 24
Finished Jul 18 04:44:17 PM PDT 24
Peak memory 183368 kb
Host smart-f2e1f928-57aa-4302-aa4e-e70c94a200f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342425197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3342425197
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2834792013
Short name T420
Test name
Test status
Simulation time 54811495283 ps
CPU time 96.55 seconds
Started Jul 18 04:43:02 PM PDT 24
Finished Jul 18 04:44:40 PM PDT 24
Peak memory 193484 kb
Host smart-a8c166a9-039f-45f6-abbb-c00f362f99e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834792013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2834792013
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.4157136900
Short name T153
Test name
Test status
Simulation time 218504294859 ps
CPU time 342.77 seconds
Started Jul 18 04:43:07 PM PDT 24
Finished Jul 18 04:48:51 PM PDT 24
Peak memory 191584 kb
Host smart-32b5e3b0-0750-4240-8abd-1677a88b0c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157136900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.4157136900
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.323593490
Short name T407
Test name
Test status
Simulation time 150580473844 ps
CPU time 43.59 seconds
Started Jul 18 04:43:06 PM PDT 24
Finished Jul 18 04:43:51 PM PDT 24
Peak memory 183360 kb
Host smart-f8fff4c0-bc7b-4387-804b-4f07afb27e2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323593490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.323593490
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2913065136
Short name T1
Test name
Test status
Simulation time 28070196534 ps
CPU time 40.99 seconds
Started Jul 18 04:43:17 PM PDT 24
Finished Jul 18 04:43:59 PM PDT 24
Peak memory 183352 kb
Host smart-11d15d6b-1104-401d-a410-e1ba114074bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913065136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2913065136
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2155034997
Short name T58
Test name
Test status
Simulation time 14599805687 ps
CPU time 23.68 seconds
Started Jul 18 04:43:01 PM PDT 24
Finished Jul 18 04:43:27 PM PDT 24
Peak memory 183764 kb
Host smart-d457405f-0163-42ab-8815-8b2a81709efe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155034997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2155034997
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2928650725
Short name T404
Test name
Test status
Simulation time 377333502504 ps
CPU time 284.28 seconds
Started Jul 18 04:43:09 PM PDT 24
Finished Jul 18 04:47:54 PM PDT 24
Peak memory 183396 kb
Host smart-355f476e-833a-46a1-9549-6bdd93914279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928650725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2928650725
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1817195220
Short name T142
Test name
Test status
Simulation time 37870106311 ps
CPU time 58.09 seconds
Started Jul 18 04:43:11 PM PDT 24
Finished Jul 18 04:44:11 PM PDT 24
Peak memory 183368 kb
Host smart-c9bf9561-3a6b-40be-88c5-7454b8f23b23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817195220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1817195220
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1371353236
Short name T440
Test name
Test status
Simulation time 162480009898 ps
CPU time 78.05 seconds
Started Jul 18 04:43:07 PM PDT 24
Finished Jul 18 04:44:26 PM PDT 24
Peak memory 191584 kb
Host smart-76325c87-195c-474d-971a-02ae159b6dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371353236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1371353236
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2085753497
Short name T181
Test name
Test status
Simulation time 160378862235 ps
CPU time 226.46 seconds
Started Jul 18 04:43:03 PM PDT 24
Finished Jul 18 04:46:51 PM PDT 24
Peak memory 191980 kb
Host smart-ee9be935-05aa-4713-8e8c-bf0b152c7b10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085753497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2085753497
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.659926967
Short name T210
Test name
Test status
Simulation time 292910006180 ps
CPU time 453.66 seconds
Started Jul 18 04:43:09 PM PDT 24
Finished Jul 18 04:50:44 PM PDT 24
Peak memory 183352 kb
Host smart-f978d87c-d8fc-4ac5-96e3-2f981b5def0e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659926967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.659926967
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1014113070
Short name T9
Test name
Test status
Simulation time 69657335263 ps
CPU time 48.58 seconds
Started Jul 18 04:43:05 PM PDT 24
Finished Jul 18 04:43:55 PM PDT 24
Peak memory 183364 kb
Host smart-b762b06d-03b5-440f-8935-197ba730752f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014113070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1014113070
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.4058695460
Short name T340
Test name
Test status
Simulation time 312851281524 ps
CPU time 175.81 seconds
Started Jul 18 04:43:25 PM PDT 24
Finished Jul 18 04:46:23 PM PDT 24
Peak memory 191552 kb
Host smart-94665d34-a303-4374-b32b-f715e87d51b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058695460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.4058695460
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.764035327
Short name T119
Test name
Test status
Simulation time 51858784856 ps
CPU time 96.73 seconds
Started Jul 18 04:43:01 PM PDT 24
Finished Jul 18 04:44:40 PM PDT 24
Peak memory 183352 kb
Host smart-7fda996e-fa37-45af-96de-455c3a2e9da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764035327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.764035327
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.882641322
Short name T306
Test name
Test status
Simulation time 2195109568099 ps
CPU time 2514.39 seconds
Started Jul 18 04:43:07 PM PDT 24
Finished Jul 18 05:25:03 PM PDT 24
Peak memory 196984 kb
Host smart-c7f412ef-4f7d-4fee-b8cd-12dcfefbad80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882641322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
882641322
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1208927476
Short name T432
Test name
Test status
Simulation time 2838411191 ps
CPU time 4.97 seconds
Started Jul 18 04:43:04 PM PDT 24
Finished Jul 18 04:43:11 PM PDT 24
Peak memory 183356 kb
Host smart-f0c86bfa-9e39-4118-95ea-5e390bbfb31a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208927476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1208927476
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2384135543
Short name T103
Test name
Test status
Simulation time 24690483703 ps
CPU time 25.98 seconds
Started Jul 18 04:43:09 PM PDT 24
Finished Jul 18 04:43:36 PM PDT 24
Peak memory 183384 kb
Host smart-100f11a1-5c69-491f-a90b-a0aba7a06157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384135543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2384135543
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2224011311
Short name T288
Test name
Test status
Simulation time 134140707407 ps
CPU time 142.15 seconds
Started Jul 18 04:43:04 PM PDT 24
Finished Jul 18 04:45:28 PM PDT 24
Peak memory 183392 kb
Host smart-95e54840-2858-45b5-b095-da05a0effebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224011311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2224011311
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.4289684516
Short name T63
Test name
Test status
Simulation time 72641441 ps
CPU time 0.56 seconds
Started Jul 18 04:43:06 PM PDT 24
Finished Jul 18 04:43:08 PM PDT 24
Peak memory 183120 kb
Host smart-8496a884-6a85-4def-bb80-c9adb0825774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289684516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.4289684516
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2187632725
Short name T70
Test name
Test status
Simulation time 488072828169 ps
CPU time 278.12 seconds
Started Jul 18 04:43:16 PM PDT 24
Finished Jul 18 04:47:55 PM PDT 24
Peak memory 183380 kb
Host smart-ccb7dbdf-ee29-44f7-aa26-b04830a70077
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187632725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2187632725
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3414599966
Short name T380
Test name
Test status
Simulation time 245742304450 ps
CPU time 89.31 seconds
Started Jul 18 04:43:13 PM PDT 24
Finished Jul 18 04:44:45 PM PDT 24
Peak memory 183380 kb
Host smart-349ffb5f-8797-46e8-b8a9-d6bdeb29b54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414599966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3414599966
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.70273003
Short name T323
Test name
Test status
Simulation time 108236696804 ps
CPU time 54.9 seconds
Started Jul 18 04:43:11 PM PDT 24
Finished Jul 18 04:44:08 PM PDT 24
Peak memory 183744 kb
Host smart-84f94214-ae0f-48de-b303-e3d3fc35e0d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70273003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.70273003
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.12996784
Short name T439
Test name
Test status
Simulation time 14926719 ps
CPU time 0.59 seconds
Started Jul 18 04:43:02 PM PDT 24
Finished Jul 18 04:43:05 PM PDT 24
Peak memory 183136 kb
Host smart-9d6a7aee-5df8-4bb3-a3f1-d21aa8984e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12996784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.12996784
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3718611415
Short name T297
Test name
Test status
Simulation time 188903301070 ps
CPU time 363.06 seconds
Started Jul 18 04:43:08 PM PDT 24
Finished Jul 18 04:49:13 PM PDT 24
Peak memory 191552 kb
Host smart-0710c955-eae3-4df1-ba5d-b7e810cf0301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718611415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3718611415
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1706940362
Short name T355
Test name
Test status
Simulation time 85926972931 ps
CPU time 143.89 seconds
Started Jul 18 04:43:05 PM PDT 24
Finished Jul 18 04:45:31 PM PDT 24
Peak memory 183464 kb
Host smart-42e72094-c17d-4622-895b-b2628081cf30
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706940362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1706940362
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2344153298
Short name T373
Test name
Test status
Simulation time 73677355210 ps
CPU time 30.47 seconds
Started Jul 18 04:43:04 PM PDT 24
Finished Jul 18 04:43:36 PM PDT 24
Peak memory 183352 kb
Host smart-42087ecc-c8ac-4dec-aeaa-d462a1b0500d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344153298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2344153298
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3245107318
Short name T273
Test name
Test status
Simulation time 70703557334 ps
CPU time 26.86 seconds
Started Jul 18 04:43:12 PM PDT 24
Finished Jul 18 04:43:41 PM PDT 24
Peak memory 192256 kb
Host smart-8869dc45-27be-46ec-b243-b47026ee89ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245107318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3245107318
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2043672617
Short name T136
Test name
Test status
Simulation time 67768133024 ps
CPU time 60.37 seconds
Started Jul 18 04:43:03 PM PDT 24
Finished Jul 18 04:44:05 PM PDT 24
Peak memory 195348 kb
Host smart-14141d9a-b624-4810-a261-e33c2324d293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043672617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2043672617
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.16901143
Short name T257
Test name
Test status
Simulation time 15008712539 ps
CPU time 27.49 seconds
Started Jul 18 04:43:05 PM PDT 24
Finished Jul 18 04:43:34 PM PDT 24
Peak memory 183384 kb
Host smart-bae938f4-efce-48b0-9f72-56496fedcf7f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16901143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.rv_timer_cfg_update_on_fly.16901143
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1479607684
Short name T26
Test name
Test status
Simulation time 26040397132 ps
CPU time 36.91 seconds
Started Jul 18 04:43:13 PM PDT 24
Finished Jul 18 04:43:52 PM PDT 24
Peak memory 183348 kb
Host smart-250ada37-c0f3-47eb-8330-61121a8f4651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479607684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1479607684
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.74657790
Short name T139
Test name
Test status
Simulation time 35978085461 ps
CPU time 191.92 seconds
Started Jul 18 04:43:09 PM PDT 24
Finished Jul 18 04:46:22 PM PDT 24
Peak memory 183352 kb
Host smart-15f0e438-8683-4472-a3f9-2b57354aeb3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74657790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.74657790
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2735445874
Short name T399
Test name
Test status
Simulation time 93204639 ps
CPU time 0.62 seconds
Started Jul 18 04:43:06 PM PDT 24
Finished Jul 18 04:43:08 PM PDT 24
Peak memory 183128 kb
Host smart-da091276-b5df-40dc-91a3-ebeb6384238c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735445874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2735445874
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.867784006
Short name T428
Test name
Test status
Simulation time 293220589358 ps
CPU time 361.09 seconds
Started Jul 18 04:43:15 PM PDT 24
Finished Jul 18 04:49:18 PM PDT 24
Peak memory 195840 kb
Host smart-db61d5f7-ec54-4087-af85-3c1f525e7b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867784006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
867784006
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.269082108
Short name T330
Test name
Test status
Simulation time 337490667227 ps
CPU time 503.28 seconds
Started Jul 18 04:43:13 PM PDT 24
Finished Jul 18 04:51:39 PM PDT 24
Peak memory 183340 kb
Host smart-5ee0aae1-aac7-40f8-8c57-72a33f1cbf78
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269082108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.269082108
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.576068442
Short name T372
Test name
Test status
Simulation time 885513947639 ps
CPU time 134.4 seconds
Started Jul 18 04:43:06 PM PDT 24
Finished Jul 18 04:45:22 PM PDT 24
Peak memory 183412 kb
Host smart-12419413-da6f-4f94-a827-9d5f88cbdb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576068442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.576068442
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2709386065
Short name T339
Test name
Test status
Simulation time 551291046979 ps
CPU time 103.95 seconds
Started Jul 18 04:43:11 PM PDT 24
Finished Jul 18 04:44:57 PM PDT 24
Peak memory 183352 kb
Host smart-d9404b2e-c352-46fc-97fd-12f2a998f608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709386065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2709386065
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1804946429
Short name T200
Test name
Test status
Simulation time 224431031239 ps
CPU time 149.66 seconds
Started Jul 18 04:43:11 PM PDT 24
Finished Jul 18 04:45:43 PM PDT 24
Peak memory 183400 kb
Host smart-6f4b934a-7a07-4001-916c-07deb2606eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804946429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1804946429
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1807394129
Short name T217
Test name
Test status
Simulation time 234282618753 ps
CPU time 346.07 seconds
Started Jul 18 04:42:21 PM PDT 24
Finished Jul 18 04:48:09 PM PDT 24
Peak memory 183344 kb
Host smart-bbb018f2-ddfc-4ce6-a92b-7e2f27edb4f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807394129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1807394129
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.239596116
Short name T362
Test name
Test status
Simulation time 138097765544 ps
CPU time 57.58 seconds
Started Jul 18 04:42:46 PM PDT 24
Finished Jul 18 04:43:46 PM PDT 24
Peak memory 183376 kb
Host smart-ca94696a-b1fb-411f-9119-03d1cfdd9a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239596116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.239596116
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2063698007
Short name T390
Test name
Test status
Simulation time 1909242311 ps
CPU time 1.44 seconds
Started Jul 18 04:42:40 PM PDT 24
Finished Jul 18 04:42:44 PM PDT 24
Peak memory 183184 kb
Host smart-fb426de2-d1ca-4f81-b68b-9292d2cfd19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063698007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2063698007
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3895643122
Short name T18
Test name
Test status
Simulation time 471311233 ps
CPU time 0.81 seconds
Started Jul 18 04:42:34 PM PDT 24
Finished Jul 18 04:42:36 PM PDT 24
Peak memory 214300 kb
Host smart-b306e816-6407-4557-a776-5c5480f06c8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895643122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3895643122
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3118357539
Short name T100
Test name
Test status
Simulation time 165111943475 ps
CPU time 1733.34 seconds
Started Jul 18 04:42:24 PM PDT 24
Finished Jul 18 05:11:19 PM PDT 24
Peak memory 191548 kb
Host smart-fa091c59-f729-4093-a01b-3b5225303af9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118357539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3118357539
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.826128528
Short name T76
Test name
Test status
Simulation time 502554445379 ps
CPU time 272.97 seconds
Started Jul 18 04:43:05 PM PDT 24
Finished Jul 18 04:47:40 PM PDT 24
Peak memory 183340 kb
Host smart-a69f19ee-c833-4ff1-9346-14e4afd26426
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826128528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.826128528
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3118050289
Short name T387
Test name
Test status
Simulation time 418638441502 ps
CPU time 311.34 seconds
Started Jul 18 04:43:12 PM PDT 24
Finished Jul 18 04:48:26 PM PDT 24
Peak memory 183396 kb
Host smart-e07e1e08-f73c-4897-a32f-2f3ddd6dddcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118050289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3118050289
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.553911069
Short name T411
Test name
Test status
Simulation time 90193203563 ps
CPU time 849.66 seconds
Started Jul 18 04:43:33 PM PDT 24
Finished Jul 18 04:57:46 PM PDT 24
Peak memory 191552 kb
Host smart-c4bd9ee5-e485-49ba-b9c6-795f82b3c2f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553911069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.553911069
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.513569386
Short name T356
Test name
Test status
Simulation time 1280938101 ps
CPU time 4.87 seconds
Started Jul 18 04:43:31 PM PDT 24
Finished Jul 18 04:43:39 PM PDT 24
Peak memory 183296 kb
Host smart-8ab2351d-6eb1-4f8b-9c4b-7f88c8e6a693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513569386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.513569386
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.199209675
Short name T370
Test name
Test status
Simulation time 69109581 ps
CPU time 0.54 seconds
Started Jul 18 04:43:05 PM PDT 24
Finished Jul 18 04:43:07 PM PDT 24
Peak memory 182720 kb
Host smart-d5d1f220-956d-4bbe-8ceb-5a03c12cbedf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199209675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
199209675
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2248174626
Short name T393
Test name
Test status
Simulation time 7140718971 ps
CPU time 12.43 seconds
Started Jul 18 04:43:15 PM PDT 24
Finished Jul 18 04:43:29 PM PDT 24
Peak memory 183340 kb
Host smart-ec766b8e-8711-4303-88e6-4ecfa764b5d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248174626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2248174626
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.133407554
Short name T359
Test name
Test status
Simulation time 94230169937 ps
CPU time 137.05 seconds
Started Jul 18 04:43:27 PM PDT 24
Finished Jul 18 04:45:47 PM PDT 24
Peak memory 183364 kb
Host smart-8a7ebec3-c534-4032-b830-2f7509dcd0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133407554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.133407554
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.4116506111
Short name T150
Test name
Test status
Simulation time 63808595481 ps
CPU time 523.07 seconds
Started Jul 18 04:43:12 PM PDT 24
Finished Jul 18 04:51:58 PM PDT 24
Peak memory 191560 kb
Host smart-dea1cd0f-ae22-4f61-a820-fb807a91875f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116506111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.4116506111
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1129106204
Short name T369
Test name
Test status
Simulation time 110413175 ps
CPU time 1.44 seconds
Started Jul 18 04:43:11 PM PDT 24
Finished Jul 18 04:43:14 PM PDT 24
Peak memory 183300 kb
Host smart-5b3924b2-935f-4e2e-93a9-20056d4fca29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129106204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1129106204
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3749822506
Short name T53
Test name
Test status
Simulation time 127151505578 ps
CPU time 105.89 seconds
Started Jul 18 04:43:13 PM PDT 24
Finished Jul 18 04:45:01 PM PDT 24
Peak memory 193720 kb
Host smart-b372ddcd-5c57-439f-93de-6ac95eeddf7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749822506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3749822506
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1084878273
Short name T302
Test name
Test status
Simulation time 325508287600 ps
CPU time 316.32 seconds
Started Jul 18 04:43:11 PM PDT 24
Finished Jul 18 04:48:29 PM PDT 24
Peak memory 183340 kb
Host smart-65a2a0f8-a606-4cdb-af00-ceb0ae8daeac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084878273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1084878273
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_random.193479079
Short name T127
Test name
Test status
Simulation time 52109900289 ps
CPU time 283.77 seconds
Started Jul 18 04:43:08 PM PDT 24
Finished Jul 18 04:47:53 PM PDT 24
Peak memory 191552 kb
Host smart-cbad1f8c-d7c2-488e-b174-4c0e871de7d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193479079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.193479079
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3826177583
Short name T160
Test name
Test status
Simulation time 32308717972 ps
CPU time 60.24 seconds
Started Jul 18 04:43:22 PM PDT 24
Finished Jul 18 04:44:25 PM PDT 24
Peak memory 191576 kb
Host smart-af197ce2-101d-4d02-b466-81ff4c2e4c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826177583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3826177583
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.182978458
Short name T228
Test name
Test status
Simulation time 866184434098 ps
CPU time 1345.97 seconds
Started Jul 18 04:43:12 PM PDT 24
Finished Jul 18 05:05:41 PM PDT 24
Peak memory 191548 kb
Host smart-935efc27-4a53-48ac-bca3-51d7d68df828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182978458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
182978458
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.2765211914
Short name T38
Test name
Test status
Simulation time 13561223568 ps
CPU time 122.71 seconds
Started Jul 18 04:43:23 PM PDT 24
Finished Jul 18 04:45:28 PM PDT 24
Peak memory 196848 kb
Host smart-b7b45c9f-93b9-4108-b10d-2be77867afcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765211914 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.2765211914
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2033972650
Short name T377
Test name
Test status
Simulation time 338826372682 ps
CPU time 139.74 seconds
Started Jul 18 04:43:09 PM PDT 24
Finished Jul 18 04:45:30 PM PDT 24
Peak memory 183348 kb
Host smart-f2ece421-2d90-4da9-ba03-a4fa9d0d625c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033972650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2033972650
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.690929035
Short name T317
Test name
Test status
Simulation time 64235218023 ps
CPU time 71.69 seconds
Started Jul 18 04:43:06 PM PDT 24
Finished Jul 18 04:44:19 PM PDT 24
Peak memory 191552 kb
Host smart-15c72d58-7924-4f70-8cd7-4007d551a5f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690929035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.690929035
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.342889719
Short name T303
Test name
Test status
Simulation time 147063462452 ps
CPU time 1263.46 seconds
Started Jul 18 04:43:23 PM PDT 24
Finished Jul 18 05:04:29 PM PDT 24
Peak memory 191580 kb
Host smart-f855a50d-9ee1-42b6-ac41-a3dfa58a94bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342889719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.342889719
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1130881929
Short name T23
Test name
Test status
Simulation time 542662145796 ps
CPU time 749.19 seconds
Started Jul 18 04:43:24 PM PDT 24
Finished Jul 18 04:55:55 PM PDT 24
Peak memory 196096 kb
Host smart-ebd2fb04-00c4-4c55-9846-3aad40a74aef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130881929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1130881929
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.134059611
Short name T155
Test name
Test status
Simulation time 143742308832 ps
CPU time 135.5 seconds
Started Jul 18 04:43:20 PM PDT 24
Finished Jul 18 04:45:38 PM PDT 24
Peak memory 183352 kb
Host smart-51296e7a-db7c-4079-b243-dc1f9aedc49f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134059611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.134059611
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2596282575
Short name T383
Test name
Test status
Simulation time 394927598054 ps
CPU time 162.34 seconds
Started Jul 18 04:43:34 PM PDT 24
Finished Jul 18 04:46:19 PM PDT 24
Peak memory 183364 kb
Host smart-a68b328b-ca72-40b6-b8b6-f1a1fbaf8b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596282575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2596282575
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.2892967366
Short name T133
Test name
Test status
Simulation time 1322633031509 ps
CPU time 658.05 seconds
Started Jul 18 04:43:21 PM PDT 24
Finished Jul 18 04:54:22 PM PDT 24
Peak memory 191544 kb
Host smart-000cd945-3554-41bd-8f34-c7053e73701a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892967366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2892967366
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3566097528
Short name T294
Test name
Test status
Simulation time 78831473563 ps
CPU time 133.15 seconds
Started Jul 18 04:43:09 PM PDT 24
Finished Jul 18 04:45:24 PM PDT 24
Peak memory 183344 kb
Host smart-c3e0c84e-d8f9-4178-9771-81f2c6cfd235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566097528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3566097528
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1985949675
Short name T251
Test name
Test status
Simulation time 79707033763 ps
CPU time 35.27 seconds
Started Jul 18 04:43:18 PM PDT 24
Finished Jul 18 04:43:55 PM PDT 24
Peak memory 191552 kb
Host smart-8bc800f1-83ac-4aeb-bef2-94c69c9aa231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985949675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1985949675
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1711580751
Short name T371
Test name
Test status
Simulation time 66768047646 ps
CPU time 80.09 seconds
Started Jul 18 04:43:18 PM PDT 24
Finished Jul 18 04:44:40 PM PDT 24
Peak memory 183356 kb
Host smart-3d4df2af-b25c-446f-9ebc-01a343d75596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711580751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1711580751
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1546291282
Short name T243
Test name
Test status
Simulation time 116614003921 ps
CPU time 111.06 seconds
Started Jul 18 04:43:21 PM PDT 24
Finished Jul 18 04:45:14 PM PDT 24
Peak memory 191552 kb
Host smart-640065db-9144-4de3-85aa-dbf7b09fddbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546291282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1546291282
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2112048791
Short name T73
Test name
Test status
Simulation time 18505326798 ps
CPU time 17.61 seconds
Started Jul 18 04:43:31 PM PDT 24
Finished Jul 18 04:43:52 PM PDT 24
Peak memory 183372 kb
Host smart-d275acf4-69e5-40a8-ae76-cda4c3a9fadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112048791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2112048791
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3502237812
Short name T389
Test name
Test status
Simulation time 858506776596 ps
CPU time 103.49 seconds
Started Jul 18 04:43:13 PM PDT 24
Finished Jul 18 04:44:59 PM PDT 24
Peak memory 183396 kb
Host smart-fc5e7705-7058-4303-86b0-1517e4a80e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502237812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3502237812
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.338920771
Short name T249
Test name
Test status
Simulation time 149639470855 ps
CPU time 246.81 seconds
Started Jul 18 04:43:15 PM PDT 24
Finished Jul 18 04:47:24 PM PDT 24
Peak memory 191592 kb
Host smart-3c47b63f-6fec-492e-9a20-8b2788f02978
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338920771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.338920771
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2958216598
Short name T11
Test name
Test status
Simulation time 24587153933 ps
CPU time 37.01 seconds
Started Jul 18 04:43:11 PM PDT 24
Finished Jul 18 04:43:51 PM PDT 24
Peak memory 191600 kb
Host smart-cbab8d7f-f9e5-45b8-8ef3-db06f6536b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958216598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2958216598
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1467295201
Short name T225
Test name
Test status
Simulation time 132872315632 ps
CPU time 209.11 seconds
Started Jul 18 04:43:33 PM PDT 24
Finished Jul 18 04:47:06 PM PDT 24
Peak memory 183352 kb
Host smart-fb0740db-5cf9-4978-af37-fd9d46e9355a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467295201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1467295201
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1215256969
Short name T438
Test name
Test status
Simulation time 79815724896 ps
CPU time 20.45 seconds
Started Jul 18 04:43:10 PM PDT 24
Finished Jul 18 04:43:32 PM PDT 24
Peak memory 183392 kb
Host smart-6517c28a-ea72-4602-9d93-b77270c98cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215256969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1215256969
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.317441217
Short name T299
Test name
Test status
Simulation time 42738630853 ps
CPU time 120.81 seconds
Started Jul 18 04:43:10 PM PDT 24
Finished Jul 18 04:45:13 PM PDT 24
Peak memory 191560 kb
Host smart-2d0c083b-20d3-475b-9ab3-dfa4fe4f8d0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317441217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.317441217
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2495508555
Short name T41
Test name
Test status
Simulation time 57572419 ps
CPU time 0.63 seconds
Started Jul 18 04:43:02 PM PDT 24
Finished Jul 18 04:43:04 PM PDT 24
Peak memory 183104 kb
Host smart-326a596f-7d71-4afc-b93b-c80c4e7a261c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495508555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2495508555
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1448672930
Short name T212
Test name
Test status
Simulation time 302462840154 ps
CPU time 482.89 seconds
Started Jul 18 04:43:17 PM PDT 24
Finished Jul 18 04:51:22 PM PDT 24
Peak memory 183352 kb
Host smart-37a03ac6-87e3-4f3c-a260-8f601766fae3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448672930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1448672930
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1188106970
Short name T415
Test name
Test status
Simulation time 168159836099 ps
CPU time 71.29 seconds
Started Jul 18 04:43:24 PM PDT 24
Finished Jul 18 04:44:38 PM PDT 24
Peak memory 183348 kb
Host smart-4dad96bf-f8c6-47c3-afff-08897ea975e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188106970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1188106970
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3940079658
Short name T320
Test name
Test status
Simulation time 261897557924 ps
CPU time 131.74 seconds
Started Jul 18 04:43:31 PM PDT 24
Finished Jul 18 04:45:45 PM PDT 24
Peak memory 191592 kb
Host smart-f975bbc5-387b-4785-9736-b6fb738cc116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940079658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3940079658
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2936634177
Short name T301
Test name
Test status
Simulation time 6530190984 ps
CPU time 11.69 seconds
Started Jul 18 04:44:15 PM PDT 24
Finished Jul 18 04:44:27 PM PDT 24
Peak memory 183448 kb
Host smart-10ebc0cf-dcf4-4dbd-b72d-edb28b93d9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936634177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2936634177
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.387011272
Short name T33
Test name
Test status
Simulation time 49185298 ps
CPU time 0.62 seconds
Started Jul 18 04:43:17 PM PDT 24
Finished Jul 18 04:43:18 PM PDT 24
Peak memory 183124 kb
Host smart-bc4176d2-bd1a-441e-86d1-b4eac7f3076b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387011272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
387011272
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2382795717
Short name T344
Test name
Test status
Simulation time 22058708312 ps
CPU time 12.12 seconds
Started Jul 18 04:43:19 PM PDT 24
Finished Jul 18 04:43:33 PM PDT 24
Peak memory 183336 kb
Host smart-c2c4dbc6-a56a-4f8a-ab9e-5871a50c3286
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382795717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2382795717
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.972784928
Short name T376
Test name
Test status
Simulation time 510776701763 ps
CPU time 86.22 seconds
Started Jul 18 04:43:31 PM PDT 24
Finished Jul 18 04:45:00 PM PDT 24
Peak memory 183368 kb
Host smart-3f59f955-6cbc-4361-aa3a-fc6e006feb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972784928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.972784928
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2655411274
Short name T224
Test name
Test status
Simulation time 204958089948 ps
CPU time 512.58 seconds
Started Jul 18 04:43:28 PM PDT 24
Finished Jul 18 04:52:04 PM PDT 24
Peak memory 193876 kb
Host smart-01e9f3ef-3038-4be4-8879-18bc2ec89950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655411274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2655411274
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2576339924
Short name T379
Test name
Test status
Simulation time 1258799073 ps
CPU time 1.02 seconds
Started Jul 18 04:43:30 PM PDT 24
Finished Jul 18 04:43:34 PM PDT 24
Peak memory 183252 kb
Host smart-4b1e15a2-2312-4662-95db-5e9721627b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576339924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2576339924
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2963937698
Short name T169
Test name
Test status
Simulation time 21069201535 ps
CPU time 10.59 seconds
Started Jul 18 04:42:32 PM PDT 24
Finished Jul 18 04:42:44 PM PDT 24
Peak memory 183256 kb
Host smart-10f82d47-f624-4e9d-a504-fa9b13e88b62
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963937698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2963937698
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2443523001
Short name T406
Test name
Test status
Simulation time 48328756412 ps
CPU time 64.68 seconds
Started Jul 18 04:42:26 PM PDT 24
Finished Jul 18 04:43:33 PM PDT 24
Peak memory 183344 kb
Host smart-d209a230-1895-4f07-a437-83d8a930158e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443523001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2443523001
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2360650675
Short name T417
Test name
Test status
Simulation time 372521462785 ps
CPU time 233.4 seconds
Started Jul 18 04:42:30 PM PDT 24
Finished Jul 18 04:46:25 PM PDT 24
Peak memory 183400 kb
Host smart-4a171d99-a4ae-436e-9a3d-016d81eaef39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360650675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2360650675
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2082320537
Short name T130
Test name
Test status
Simulation time 39801088291 ps
CPU time 71.22 seconds
Started Jul 18 04:42:27 PM PDT 24
Finished Jul 18 04:43:40 PM PDT 24
Peak memory 183408 kb
Host smart-e166498c-b240-465b-b3ee-1fe37565ee6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082320537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2082320537
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1647656412
Short name T283
Test name
Test status
Simulation time 96800836944 ps
CPU time 376.21 seconds
Started Jul 18 04:42:38 PM PDT 24
Finished Jul 18 04:48:57 PM PDT 24
Peak memory 191576 kb
Host smart-e59646ba-a7dd-4912-a191-cfaf8d7a5c45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647656412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1647656412
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.1771502143
Short name T326
Test name
Test status
Simulation time 107597768603 ps
CPU time 410.07 seconds
Started Jul 18 04:43:21 PM PDT 24
Finished Jul 18 04:50:13 PM PDT 24
Peak memory 191976 kb
Host smart-3722666d-8e53-4e3f-9dcc-ef79fb8db4ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771502143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1771502143
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.96657573
Short name T289
Test name
Test status
Simulation time 69331340580 ps
CPU time 256.03 seconds
Started Jul 18 04:43:27 PM PDT 24
Finished Jul 18 04:47:46 PM PDT 24
Peak memory 191592 kb
Host smart-0ccacab2-7619-4f06-bc6e-08bb11a6c4b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96657573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.96657573
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3249361653
Short name T222
Test name
Test status
Simulation time 393229369508 ps
CPU time 922.67 seconds
Started Jul 18 04:43:41 PM PDT 24
Finished Jul 18 04:59:05 PM PDT 24
Peak memory 191560 kb
Host smart-43e3756b-b078-4976-8997-5a2fa43440cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249361653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3249361653
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3839195545
Short name T77
Test name
Test status
Simulation time 205404057279 ps
CPU time 394.3 seconds
Started Jul 18 04:43:31 PM PDT 24
Finished Jul 18 04:50:08 PM PDT 24
Peak memory 191592 kb
Host smart-92c3996d-d9ad-4cee-9bbe-44d33763d219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839195545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3839195545
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3918650669
Short name T337
Test name
Test status
Simulation time 1585629564533 ps
CPU time 866.45 seconds
Started Jul 18 04:43:27 PM PDT 24
Finished Jul 18 04:57:56 PM PDT 24
Peak memory 191956 kb
Host smart-c030f5c4-28e4-41ce-be9a-2bbd240b9cfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918650669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3918650669
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.4132581937
Short name T241
Test name
Test status
Simulation time 202143430778 ps
CPU time 1732.94 seconds
Started Jul 18 04:43:15 PM PDT 24
Finished Jul 18 05:12:10 PM PDT 24
Peak memory 183356 kb
Host smart-a6b34fd5-b3a0-41e9-959d-91b5f9f9e1fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132581937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.4132581937
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.4015106827
Short name T54
Test name
Test status
Simulation time 16076652853 ps
CPU time 6.73 seconds
Started Jul 18 04:43:31 PM PDT 24
Finished Jul 18 04:43:40 PM PDT 24
Peak memory 183352 kb
Host smart-7b8f0509-e34e-49c4-a18c-0e4a32b9235c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015106827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.4015106827
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.989426020
Short name T233
Test name
Test status
Simulation time 420550950204 ps
CPU time 252.92 seconds
Started Jul 18 04:42:26 PM PDT 24
Finished Jul 18 04:46:41 PM PDT 24
Peak memory 183360 kb
Host smart-fba88270-e9ad-40f2-bb6c-99b2b63e15c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989426020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.989426020
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1697146340
Short name T44
Test name
Test status
Simulation time 758967151014 ps
CPU time 137.14 seconds
Started Jul 18 04:42:29 PM PDT 24
Finished Jul 18 04:44:48 PM PDT 24
Peak memory 183352 kb
Host smart-bd4abe9a-b936-4f00-b0cc-fb32128c5305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697146340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1697146340
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.4290234399
Short name T159
Test name
Test status
Simulation time 385143175171 ps
CPU time 1126.88 seconds
Started Jul 18 04:42:28 PM PDT 24
Finished Jul 18 05:01:17 PM PDT 24
Peak memory 191592 kb
Host smart-74eff796-da26-46b5-b605-7f75d0dd9e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290234399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4290234399
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.489781920
Short name T394
Test name
Test status
Simulation time 561376732161 ps
CPU time 227.28 seconds
Started Jul 18 04:42:38 PM PDT 24
Finished Jul 18 04:46:28 PM PDT 24
Peak memory 194872 kb
Host smart-8c2c471b-0c11-4e4b-aee9-c493df4144d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489781920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.489781920
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.3637460428
Short name T405
Test name
Test status
Simulation time 216739376743 ps
CPU time 618.39 seconds
Started Jul 18 04:42:28 PM PDT 24
Finished Jul 18 04:52:49 PM PDT 24
Peak memory 208400 kb
Host smart-9205cc9b-d71f-4b3c-b18e-228eaaab5152
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637460428 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.3637460428
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.rv_timer_random.4041281898
Short name T232
Test name
Test status
Simulation time 599998975107 ps
CPU time 488.68 seconds
Started Jul 18 04:43:26 PM PDT 24
Finished Jul 18 04:51:37 PM PDT 24
Peak memory 191568 kb
Host smart-6d76abfc-349a-4b3d-83f1-6b4c2c6f245f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041281898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.4041281898
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1337427973
Short name T408
Test name
Test status
Simulation time 344845371877 ps
CPU time 86.26 seconds
Started Jul 18 04:43:20 PM PDT 24
Finished Jul 18 04:44:48 PM PDT 24
Peak memory 191664 kb
Host smart-af9c48dd-2b4a-4ad6-a20a-6462dd484f1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337427973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1337427973
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.820837535
Short name T226
Test name
Test status
Simulation time 16643844575 ps
CPU time 24.63 seconds
Started Jul 18 04:43:27 PM PDT 24
Finished Jul 18 04:43:55 PM PDT 24
Peak memory 183360 kb
Host smart-3d5f0326-9dff-4f70-aac9-7d8cc0c6c60a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820837535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.820837535
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.450484602
Short name T163
Test name
Test status
Simulation time 2826460062942 ps
CPU time 881.95 seconds
Started Jul 18 04:43:12 PM PDT 24
Finished Jul 18 04:57:57 PM PDT 24
Peak memory 191684 kb
Host smart-a81ccc71-9674-4f9c-b890-df2455221c68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450484602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.450484602
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.4119153459
Short name T147
Test name
Test status
Simulation time 93800303488 ps
CPU time 563.17 seconds
Started Jul 18 04:43:24 PM PDT 24
Finished Jul 18 04:52:50 PM PDT 24
Peak memory 191564 kb
Host smart-51b884a3-2276-42da-92dd-16790c09ff4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119153459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.4119153459
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2249161073
Short name T183
Test name
Test status
Simulation time 157432576122 ps
CPU time 271.81 seconds
Started Jul 18 04:43:27 PM PDT 24
Finished Jul 18 04:48:02 PM PDT 24
Peak memory 193784 kb
Host smart-d353655a-8745-4c50-ba8f-cfd024cf8a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249161073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2249161073
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.642417286
Short name T272
Test name
Test status
Simulation time 28745250140 ps
CPU time 51.35 seconds
Started Jul 18 04:43:21 PM PDT 24
Finished Jul 18 04:44:14 PM PDT 24
Peak memory 191676 kb
Host smart-9918b655-3807-4ba1-8e3d-ac84a2f5c341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642417286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.642417286
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.715797435
Short name T185
Test name
Test status
Simulation time 130770246089 ps
CPU time 220.65 seconds
Started Jul 18 04:43:26 PM PDT 24
Finished Jul 18 04:47:10 PM PDT 24
Peak memory 191552 kb
Host smart-391c3d8f-ac6e-409c-8927-f5222e7c750d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715797435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.715797435
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.759735919
Short name T345
Test name
Test status
Simulation time 4274555789 ps
CPU time 7.23 seconds
Started Jul 18 04:42:25 PM PDT 24
Finished Jul 18 04:42:35 PM PDT 24
Peak memory 183336 kb
Host smart-ceeeaa6e-edf2-4eb2-b956-508d4ebae985
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759735919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.759735919
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.4150131811
Short name T414
Test name
Test status
Simulation time 636879015226 ps
CPU time 199.23 seconds
Started Jul 18 04:42:25 PM PDT 24
Finished Jul 18 04:45:46 PM PDT 24
Peak memory 183400 kb
Host smart-7b8b6c92-7b50-46d0-a62c-4f67524f0dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150131811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.4150131811
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3148460037
Short name T260
Test name
Test status
Simulation time 848944181905 ps
CPU time 226.44 seconds
Started Jul 18 04:42:24 PM PDT 24
Finished Jul 18 04:46:13 PM PDT 24
Peak memory 191560 kb
Host smart-af7ba0b4-cb84-4cfb-ae84-6c6c7278ccb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148460037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3148460037
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2980232807
Short name T396
Test name
Test status
Simulation time 139209327965 ps
CPU time 56.56 seconds
Started Jul 18 04:42:23 PM PDT 24
Finished Jul 18 04:43:21 PM PDT 24
Peak memory 183352 kb
Host smart-856a8198-d586-45db-87be-0d5d03851bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980232807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2980232807
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3278130045
Short name T450
Test name
Test status
Simulation time 52128656714 ps
CPU time 289.35 seconds
Started Jul 18 04:42:25 PM PDT 24
Finished Jul 18 04:47:17 PM PDT 24
Peak memory 195008 kb
Host smart-d32b0943-baec-410f-b760-8205aa2193cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278130045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3278130045
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.4160289770
Short name T209
Test name
Test status
Simulation time 41119749727 ps
CPU time 60.39 seconds
Started Jul 18 04:43:24 PM PDT 24
Finished Jul 18 04:44:27 PM PDT 24
Peak memory 195400 kb
Host smart-939dbe54-edec-46cf-a76a-2c5af02f7a2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160289770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.4160289770
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.612624327
Short name T245
Test name
Test status
Simulation time 269850686767 ps
CPU time 175.03 seconds
Started Jul 18 04:43:23 PM PDT 24
Finished Jul 18 04:46:20 PM PDT 24
Peak memory 191544 kb
Host smart-bccf886a-1858-4935-9bad-9e08a0917c31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612624327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.612624327
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2012680882
Short name T250
Test name
Test status
Simulation time 97868652845 ps
CPU time 219.74 seconds
Started Jul 18 04:43:39 PM PDT 24
Finished Jul 18 04:47:20 PM PDT 24
Peak memory 191556 kb
Host smart-36468bcc-43b2-44ca-b7d2-859be8902d70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012680882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2012680882
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2844571797
Short name T398
Test name
Test status
Simulation time 8546278925 ps
CPU time 98.7 seconds
Started Jul 18 04:43:22 PM PDT 24
Finished Jul 18 04:45:03 PM PDT 24
Peak memory 183336 kb
Host smart-22959c7b-a523-4a17-bc5b-395b4cb21736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844571797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2844571797
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1850621516
Short name T187
Test name
Test status
Simulation time 663378685222 ps
CPU time 515.72 seconds
Started Jul 18 04:43:25 PM PDT 24
Finished Jul 18 04:52:04 PM PDT 24
Peak memory 191528 kb
Host smart-05efcfed-9b33-409f-b311-5d8d42fed679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850621516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1850621516
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2465014224
Short name T240
Test name
Test status
Simulation time 88902577418 ps
CPU time 333.7 seconds
Started Jul 18 04:43:16 PM PDT 24
Finished Jul 18 04:48:51 PM PDT 24
Peak memory 191568 kb
Host smart-402fe605-2a8c-4304-ad49-17165e3ae43b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465014224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2465014224
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2240874949
Short name T296
Test name
Test status
Simulation time 71270194527 ps
CPU time 681.31 seconds
Started Jul 18 04:43:18 PM PDT 24
Finished Jul 18 04:54:41 PM PDT 24
Peak memory 191580 kb
Host smart-2a2e51a0-bd4a-4510-bc98-1da22bf10f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240874949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2240874949
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3382228992
Short name T424
Test name
Test status
Simulation time 51387034982 ps
CPU time 75.77 seconds
Started Jul 18 04:43:29 PM PDT 24
Finished Jul 18 04:44:48 PM PDT 24
Peak memory 183392 kb
Host smart-9dfd4118-6229-49eb-863e-7c6dbcfc338e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382228992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3382228992
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1972892047
Short name T418
Test name
Test status
Simulation time 708454184019 ps
CPU time 2153.07 seconds
Started Jul 18 04:43:24 PM PDT 24
Finished Jul 18 05:19:21 PM PDT 24
Peak memory 191672 kb
Host smart-cc238acf-33f0-4d1f-a3da-a8a9807a99f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972892047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1972892047
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3623513651
Short name T253
Test name
Test status
Simulation time 705755285269 ps
CPU time 820.1 seconds
Started Jul 18 04:42:28 PM PDT 24
Finished Jul 18 04:56:11 PM PDT 24
Peak memory 183396 kb
Host smart-7c843fbf-058b-453c-85e6-0cfcba216158
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623513651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3623513651
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3589276768
Short name T374
Test name
Test status
Simulation time 23254634122 ps
CPU time 35.83 seconds
Started Jul 18 04:42:27 PM PDT 24
Finished Jul 18 04:43:05 PM PDT 24
Peak memory 183364 kb
Host smart-62592049-8355-4015-926f-6fd600d5c167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589276768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3589276768
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3251961518
Short name T313
Test name
Test status
Simulation time 26046140604 ps
CPU time 40.06 seconds
Started Jul 18 04:42:35 PM PDT 24
Finished Jul 18 04:43:16 PM PDT 24
Peak memory 183312 kb
Host smart-99a18703-60fe-466b-ae3f-94b8400523ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251961518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3251961518
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2536487830
Short name T168
Test name
Test status
Simulation time 36708269810 ps
CPU time 26.81 seconds
Started Jul 18 04:42:32 PM PDT 24
Finished Jul 18 04:43:00 PM PDT 24
Peak memory 191608 kb
Host smart-5ec032c9-b092-46dd-b295-607daa1a21bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536487830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2536487830
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/81.rv_timer_random.679409023
Short name T437
Test name
Test status
Simulation time 246714168900 ps
CPU time 347.27 seconds
Started Jul 18 04:43:26 PM PDT 24
Finished Jul 18 04:49:16 PM PDT 24
Peak memory 191552 kb
Host smart-3c1bc2e8-bd0f-4e46-a056-1563c20d6999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679409023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.679409023
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.308427639
Short name T350
Test name
Test status
Simulation time 415904300158 ps
CPU time 151.07 seconds
Started Jul 18 04:43:35 PM PDT 24
Finished Jul 18 04:46:10 PM PDT 24
Peak memory 195408 kb
Host smart-128e4a28-1f4b-4144-a431-11e7a0370052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308427639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.308427639
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.4271003963
Short name T335
Test name
Test status
Simulation time 190067788089 ps
CPU time 886.54 seconds
Started Jul 18 04:43:23 PM PDT 24
Finished Jul 18 04:58:12 PM PDT 24
Peak memory 191568 kb
Host smart-d3a9b25a-cf01-422d-8b90-0686f89e024d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271003963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.4271003963
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2133338799
Short name T403
Test name
Test status
Simulation time 130048137216 ps
CPU time 57.49 seconds
Started Jul 18 04:43:27 PM PDT 24
Finished Jul 18 04:44:27 PM PDT 24
Peak memory 191976 kb
Host smart-bc03824e-dbd2-4203-a2c2-843cd6ebc7d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133338799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2133338799
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2450344941
Short name T291
Test name
Test status
Simulation time 798263107685 ps
CPU time 393.81 seconds
Started Jul 18 04:42:36 PM PDT 24
Finished Jul 18 04:49:11 PM PDT 24
Peak memory 183336 kb
Host smart-5e462beb-8ae2-43af-a4ec-9d6c5b53b3c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450344941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2450344941
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1568804685
Short name T386
Test name
Test status
Simulation time 38619521463 ps
CPU time 15.55 seconds
Started Jul 18 04:42:27 PM PDT 24
Finished Jul 18 04:42:45 PM PDT 24
Peak memory 183352 kb
Host smart-72e9454d-c69f-4299-baeb-2d67171d060b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568804685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1568804685
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.417365412
Short name T137
Test name
Test status
Simulation time 54772415363 ps
CPU time 411.78 seconds
Started Jul 18 04:42:27 PM PDT 24
Finished Jul 18 04:49:21 PM PDT 24
Peak memory 191976 kb
Host smart-56abdffe-67cb-4b5d-994d-1f45babc2825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417365412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.417365412
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2812548088
Short name T101
Test name
Test status
Simulation time 32859995975 ps
CPU time 14.06 seconds
Started Jul 18 04:42:39 PM PDT 24
Finished Jul 18 04:42:56 PM PDT 24
Peak memory 191572 kb
Host smart-a0eb86eb-5a33-468d-a705-9d44a502adfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812548088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2812548088
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.648252881
Short name T156
Test name
Test status
Simulation time 372937151388 ps
CPU time 168.48 seconds
Started Jul 18 04:42:26 PM PDT 24
Finished Jul 18 04:45:17 PM PDT 24
Peak memory 183356 kb
Host smart-ccbfe350-9f28-4051-ab33-33dd303be949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648252881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.648252881
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.3843489533
Short name T171
Test name
Test status
Simulation time 351779239319 ps
CPU time 334.05 seconds
Started Jul 18 04:43:40 PM PDT 24
Finished Jul 18 04:49:15 PM PDT 24
Peak memory 194044 kb
Host smart-20ed12c6-e5f8-4bd2-a3c7-0db79f5a4e25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843489533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3843489533
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.4162622945
Short name T202
Test name
Test status
Simulation time 121177389668 ps
CPU time 185.72 seconds
Started Jul 18 04:43:38 PM PDT 24
Finished Jul 18 04:46:46 PM PDT 24
Peak memory 191352 kb
Host smart-64112c2d-b33c-4444-9342-ba0b978e5ef3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162622945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.4162622945
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3811962765
Short name T259
Test name
Test status
Simulation time 255710847720 ps
CPU time 1235.72 seconds
Started Jul 18 04:43:28 PM PDT 24
Finished Jul 18 05:04:06 PM PDT 24
Peak memory 191596 kb
Host smart-a878cb8c-3a62-493e-8e61-3edd8e8edd5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811962765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3811962765
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3512645701
Short name T444
Test name
Test status
Simulation time 316462639933 ps
CPU time 147.83 seconds
Started Jul 18 04:43:18 PM PDT 24
Finished Jul 18 04:45:47 PM PDT 24
Peak memory 191348 kb
Host smart-3d689fd8-6f7e-4440-861c-f57e4a9fc72b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512645701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3512645701
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1416783081
Short name T231
Test name
Test status
Simulation time 419705622006 ps
CPU time 308.13 seconds
Started Jul 18 04:43:47 PM PDT 24
Finished Jul 18 04:48:58 PM PDT 24
Peak memory 191564 kb
Host smart-1c89705c-704f-4110-b16a-b876bb2837e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416783081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1416783081
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1336269186
Short name T254
Test name
Test status
Simulation time 15359286394 ps
CPU time 10.95 seconds
Started Jul 18 04:43:33 PM PDT 24
Finished Jul 18 04:43:47 PM PDT 24
Peak memory 183356 kb
Host smart-81a1c22d-a0dd-4d83-9cbf-01e6da7c7b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336269186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1336269186
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.448637169
Short name T276
Test name
Test status
Simulation time 225667253119 ps
CPU time 205.66 seconds
Started Jul 18 04:43:36 PM PDT 24
Finished Jul 18 04:47:05 PM PDT 24
Peak memory 191560 kb
Host smart-527ba209-db4c-4d2b-8f2d-ec112d435a96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448637169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.448637169
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.978334420
Short name T318
Test name
Test status
Simulation time 120399373768 ps
CPU time 95.72 seconds
Started Jul 18 04:43:38 PM PDT 24
Finished Jul 18 04:45:16 PM PDT 24
Peak memory 191376 kb
Host smart-7dcdd0f9-340a-417e-97c8-deed7458e092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978334420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.978334420
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.487574903
Short name T162
Test name
Test status
Simulation time 142796198511 ps
CPU time 789.02 seconds
Started Jul 18 04:43:30 PM PDT 24
Finished Jul 18 04:56:42 PM PDT 24
Peak memory 191600 kb
Host smart-053c7019-719f-4d8e-95e2-13684a6d0078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487574903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.487574903
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3791867752
Short name T258
Test name
Test status
Simulation time 316955299938 ps
CPU time 179.4 seconds
Started Jul 18 04:43:37 PM PDT 24
Finished Jul 18 04:46:39 PM PDT 24
Peak memory 191556 kb
Host smart-0658e958-3cbc-4c9a-9506-c11fdc8bde1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791867752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3791867752
Directory /workspace/99.rv_timer_random/latest
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