Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65629860	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	67565637	1		T1	151550		T2	20079		T3	10950

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	131523650	1		T1	301563		T2	40338		T3	21460
values[0x0]	794168	1		T1	23		T2	120		T3	8
values[0x1]	877679	1		T1	30		T2	102		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52393907	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	80801590	1		T1	181815		T2	24326		T3	13005

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	380756	1		T2	174		T3	81		T5	93
valid_sources[0x01]	377349	1		T2	179		T3	87		T5	148
valid_sources[0x02]	374010	1		T2	157		T3	76		T5	123
valid_sources[0x03]	738364	1		T2	145		T3	105		T5	135
valid_sources[0x04]	376119	1		T2	160		T3	81		T5	143
valid_sources[0x05]	1498623	1		T2	154		T3	71		T5	93
valid_sources[0x06]	479170	1		T2	143		T3	74		T5	137
valid_sources[0x07]	379290	1		T2	167		T3	106		T5	99
valid_sources[0x08]	374385	1		T2	169		T3	92		T5	133
valid_sources[0x09]	375814	1		T2	161		T3	99		T5	100
valid_sources[0x0a]	378105	1		T2	147		T3	77		T5	116
valid_sources[0x0b]	375248	1		T2	163		T3	82		T5	150
valid_sources[0x0c]	475889	1		T2	179		T3	81		T5	158
valid_sources[0x0d]	396111	1		T2	138		T3	87		T5	73
valid_sources[0x0e]	910383	1		T2	161		T3	85		T5	116
valid_sources[0x0f]	374711	1		T2	146		T3	74		T5	100
valid_sources[0x10]	377014	1		T2	155		T3	72		T5	150
valid_sources[0x11]	1245324	1		T2	158		T3	103		T5	143
valid_sources[0x12]	379278	1		T2	164		T3	90		T5	99
valid_sources[0x13]	1417149	1		T2	157		T3	101		T5	93
valid_sources[0x14]	413419	1		T2	156		T3	85		T5	70
valid_sources[0x15]	738598	1		T2	163		T3	69		T5	124
valid_sources[0x16]	379426	1		T2	160		T3	91		T5	147
valid_sources[0x17]	380161	1		T2	173		T3	84		T5	79
valid_sources[0x18]	379306	1		T2	146		T3	88		T5	144
valid_sources[0x19]	375218	1		T2	158		T3	85		T5	86
valid_sources[0x1a]	895590	1		T2	151		T3	87		T5	121
valid_sources[0x1b]	432576	1		T2	163		T3	88		T5	121
valid_sources[0x1c]	379101	1		T2	143		T3	76		T5	105
valid_sources[0x1d]	392813	1		T2	173		T3	101		T5	87
valid_sources[0x1e]	375953	1		T2	135		T3	81		T5	101
valid_sources[0x1f]	3314246	1		T2	145		T3	87		T5	93
valid_sources[0x20]	376574	1		T2	150		T3	72		T5	109
valid_sources[0x21]	377902	1		T2	183		T3	82		T5	118
valid_sources[0x22]	379031	1		T2	170		T3	75		T5	134
valid_sources[0x23]	378881	1		T2	182		T3	93		T5	91
valid_sources[0x24]	439298	1		T2	149		T3	87		T5	125
valid_sources[0x25]	376448	1		T2	158		T3	91		T5	46
valid_sources[0x26]	377912	1		T2	190		T3	95		T5	97
valid_sources[0x27]	400888	1		T2	178		T3	76		T5	162
valid_sources[0x28]	402490	1		T2	187		T3	83		T5	95
valid_sources[0x29]	378679	1		T2	172		T3	83		T5	119
valid_sources[0x2a]	376413	1		T2	174		T3	80		T5	82
valid_sources[0x2b]	377194	1		T2	158		T3	83		T5	84
valid_sources[0x2c]	377810	1		T2	163		T3	84		T5	78
valid_sources[0x2d]	378050	1		T2	158		T3	81		T5	87
valid_sources[0x2e]	376475	1		T2	160		T3	112		T5	97
valid_sources[0x2f]	378148	1		T2	149		T3	93		T5	91
valid_sources[0x30]	376198	1		T2	154		T3	79		T5	81
valid_sources[0x31]	377052	1		T2	173		T3	90		T5	94
valid_sources[0x32]	377794	1		T2	183		T3	95		T5	125
valid_sources[0x33]	378111	1		T2	160		T3	93		T5	129
valid_sources[0x34]	476052	1		T2	156		T3	89		T5	139
valid_sources[0x35]	380978	1		T2	159		T3	98		T5	142
valid_sources[0x36]	380966	1		T2	166		T3	59		T5	81
valid_sources[0x37]	376843	1		T2	151		T3	65		T5	120
valid_sources[0x38]	392108	1		T2	174		T3	75		T5	178
valid_sources[0x39]	1265254	1		T2	159		T3	81		T5	92
valid_sources[0x3a]	375179	1		T2	137		T3	79		T5	73
valid_sources[0x3b]	380363	1		T2	162		T3	84		T5	94
valid_sources[0x3c]	379190	1		T2	158		T3	73		T5	131
valid_sources[0x3d]	384130	1		T2	157		T3	74		T5	62
valid_sources[0x3e]	376143	1		T2	122		T3	82		T5	122
valid_sources[0x3f]	403616	1		T2	182		T3	96		T5	106
valid_sources[0x40]	382923	1		T2	159		T3	77		T5	109
valid_sources[0x41]	715587	1		T2	141		T3	80		T5	113
valid_sources[0x42]	386498	1		T2	154		T3	81		T5	78
valid_sources[0x43]	377353	1		T2	154		T3	68		T5	131
valid_sources[0x44]	3256296	1		T2	152		T3	93		T5	84
valid_sources[0x45]	383873	1		T2	174		T3	80		T5	111
valid_sources[0x46]	376044	1		T2	156		T3	92		T5	114
valid_sources[0x47]	374444	1		T2	180		T3	64		T5	126
valid_sources[0x48]	375585	1		T2	173		T3	94		T5	140
valid_sources[0x49]	377760	1		T2	138		T3	101		T5	161
valid_sources[0x4a]	377056	1		T2	152		T3	81		T5	89
valid_sources[0x4b]	378586	1		T2	168		T3	87		T5	123
valid_sources[0x4c]	378851	1		T2	169		T3	78		T5	99
valid_sources[0x4d]	378051	1		T2	145		T3	75		T5	128
valid_sources[0x4e]	378246	1		T2	148		T3	76		T5	115
valid_sources[0x4f]	378263	1		T2	173		T3	101		T5	172
valid_sources[0x50]	377945	1		T2	158		T3	59		T5	104
valid_sources[0x51]	478767	1		T2	165		T3	72		T5	111
valid_sources[0x52]	599547	1		T2	141		T3	76		T5	92
valid_sources[0x53]	375921	1		T2	168		T3	85		T5	109
valid_sources[0x54]	379759	1		T2	155		T3	80		T5	121
valid_sources[0x55]	2100743	1		T2	136		T3	81		T5	117
valid_sources[0x56]	378900	1		T2	145		T3	75		T5	130
valid_sources[0x57]	379324	1		T2	194		T3	98		T5	113
valid_sources[0x58]	377317	1		T2	146		T3	80		T5	126
valid_sources[0x59]	375225	1		T2	142		T3	93		T5	119
valid_sources[0x5a]	380822	1		T2	159		T3	86		T5	117
valid_sources[0x5b]	378120	1		T2	189		T3	93		T5	114
valid_sources[0x5c]	450662	1		T2	133		T3	80		T5	96
valid_sources[0x5d]	400995	1		T2	146		T3	81		T5	95
valid_sources[0x5e]	392604	1		T2	144		T3	79		T5	171
valid_sources[0x5f]	1534673	1		T2	145		T3	67		T5	99
valid_sources[0x60]	768971	1		T2	156		T3	77		T5	120
valid_sources[0x61]	377097	1		T2	172		T3	100		T5	105
valid_sources[0x62]	375732	1		T2	156		T3	74		T5	114
valid_sources[0x63]	568537	1		T2	181		T3	88		T5	99
valid_sources[0x64]	377773	1		T2	150		T3	85		T5	86
valid_sources[0x65]	378497	1		T2	168		T3	82		T5	82
valid_sources[0x66]	378420	1		T2	149		T3	71		T5	144
valid_sources[0x67]	377688	1		T2	132		T3	86		T5	100
valid_sources[0x68]	377655	1		T2	164		T3	81		T5	84
valid_sources[0x69]	379558	1		T2	151		T3	94		T5	147
valid_sources[0x6a]	377425	1		T2	148		T3	71		T5	102
valid_sources[0x6b]	376171	1		T2	165		T3	71		T5	121
valid_sources[0x6c]	433545	1		T2	135		T3	78		T5	55
valid_sources[0x6d]	378496	1		T2	136		T3	72		T5	114
valid_sources[0x6e]	379737	1		T2	156		T3	103		T5	187
valid_sources[0x6f]	383162	1		T2	149		T3	64		T5	94
valid_sources[0x70]	519938	1		T2	147		T3	78		T5	87
valid_sources[0x71]	378670	1		T2	171		T3	92		T5	85
valid_sources[0x72]	377131	1		T2	173		T3	92		T5	126
valid_sources[0x73]	377608	1		T2	130		T3	80		T5	120
valid_sources[0x74]	379117	1		T2	149		T3	86		T5	89
valid_sources[0x75]	379047	1		T2	156		T3	104		T5	122
valid_sources[0x76]	376657	1		T2	165		T3	75		T5	103
valid_sources[0x77]	547127	1		T2	175		T3	95		T5	110
valid_sources[0x78]	375021	1		T2	187		T3	91		T5	130
valid_sources[0x79]	377888	1		T2	141		T3	71		T5	135
valid_sources[0x7a]	410347	1		T2	150		T3	92		T5	132
valid_sources[0x7b]	377940	1		T2	170		T3	71		T5	138
valid_sources[0x7c]	526586	1		T2	148		T3	78		T5	101
valid_sources[0x7d]	379147	1		T2	176		T3	100		T5	84
valid_sources[0x7e]	379436	1		T2	146		T3	77		T5	101
valid_sources[0x7f]	375671	1		T2	123		T3	95		T5	131
valid_sources[0x80]	460459	1		T2	165		T3	98		T5	96

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

66007767

1

T1

151509

T2

19943

T3

10941

values[0x0]

all_enables

biggest_size

780013

1

T1

19

T2

85

T3

4

values[0x1]

all_enables

biggest_size

777857

1

T1

22

T2

51

T3

5