Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2758026	0	0
cfg0_rd_A	2147483647	9019	0	0
compare_lower0_0_rd_A	2147483647	10773	0	0
compare_upper0_0_rd_A	2147483647	9175	0	0
ctrl_rd_A	2147483647	9408	0	0
intr_enable0_rd_A	2147483647	12107	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2758026	0	0
T9	472127	124536	0	0
T10	311320	0	0	0
T11	318710	0	0	0
T12	0	63131	0	0
T13	0	17599	0	0
T33	0	59059	0	0
T34	0	165305	0	0
T35	0	285389	0	0
T36	0	266198	0	0
T37	0	233153	0	0
T38	0	155570	0	0
T39	0	401359	0	0
T40	122510	0	0	0
T41	846367	0	0	0
T42	121640	0	0	0
T43	362259	0	0	0
T44	128742	0	0	0
T45	437921	0	0	0
T46	325332	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9019	0	0
T9	472127	1285	0	0
T10	311320	0	0	0
T11	318710	0	0	0
T29	0	168	0	0
T30	0	62	0	0
T36	0	2490	0	0
T37	0	1063	0	0
T39	0	2000	0	0
T40	122510	0	0	0
T41	846367	0	0	0
T42	121640	0	0	0
T43	362259	0	0	0
T44	128742	0	0	0
T45	437921	0	0	0
T46	325332	0	0	0
T47	0	1144	0	0
T48	0	8	0	0
T49	0	5	0	0
T50	0	20	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10773	0	0
T9	472127	1565	0	0
T10	311320	0	0	0
T11	318710	0	0	0
T29	0	127	0	0
T30	0	54	0	0
T36	0	3201	0	0
T37	0	1328	0	0
T39	0	2444	0	0
T40	122510	0	0	0
T41	846367	0	0	0
T42	121640	0	0	0
T43	362259	0	0	0
T44	128742	0	0	0
T45	437921	0	0	0
T46	325332	0	0	0
T47	0	1354	0	0
T49	0	6	0	0
T50	0	2	0	0
T51	0	66	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9175	0	0
T9	472127	1174	0	0
T10	311320	0	0	0
T11	318710	0	0	0
T29	0	112	0	0
T30	0	45	0	0
T36	0	2701	0	0
T37	0	1198	0	0
T39	0	2082	0	0
T40	122510	0	0	0
T41	846367	0	0	0
T42	121640	0	0	0
T43	362259	0	0	0
T44	128742	0	0	0
T45	437921	0	0	0
T46	325332	0	0	0
T47	0	1197	0	0
T49	0	9	0	0
T51	0	73	0	0
T52	0	15	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9408	0	0
T9	472127	1341	0	0
T10	311320	0	0	0
T11	318710	0	0	0
T29	0	104	0	0
T30	0	39	0	0
T36	0	2743	0	0
T37	0	1161	0	0
T39	0	2152	0	0
T40	122510	0	0	0
T41	846367	0	0	0
T42	121640	0	0	0
T43	362259	0	0	0
T44	128742	0	0	0
T45	437921	0	0	0
T46	325332	0	0	0
T47	0	1213	0	0
T49	0	11	0	0
T50	0	10	0	0
T51	0	70	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12107	0	0
T9	472127	1730	0	0
T10	311320	0	0	0
T11	318710	0	0	0
T40	122510	0	0	0
T41	846367	0	0	0
T42	121640	0	0	0
T43	362259	0	0	0
T44	128742	0	0	0
T45	437921	0	0	0
T46	325332	0	0	0
T53	0	23	0	0
T54	0	23	0	0
T55	0	61	0	0
T56	0	17	0	0
T57	0	21	0	0
T58	0	11	0	0
T59	0	67	0	0
T60	0	98	0	0
T61	0	68	0	0