Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 68025062 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 69537267 1 T1 84 T2 9925 T3 13620



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 136243273 1 T1 99 T2 19771 T3 27406
values[0x0] 627102 1 T1 54 T2 12 T3 34
values[0x1] 691954 1 T1 44 T2 14 T3 30



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 54325616 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 83236713 1 T1 95 T2 11908 T3 16335



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 427107 1 T2 89 T4 43 T6 1346
valid_sources[0x01] 427528 1 T2 94 T4 37 T6 1382
valid_sources[0x02] 426476 1 T2 68 T4 83 T6 1301
valid_sources[0x03] 426821 1 T2 53 T4 72 T6 1338
valid_sources[0x04] 426925 1 T2 92 T4 89 T6 1473
valid_sources[0x05] 427927 1 T2 107 T4 70 T6 1381
valid_sources[0x06] 427868 1 T2 72 T4 101 T6 1287
valid_sources[0x07] 429124 1 T2 63 T4 69 T6 1332
valid_sources[0x08] 427875 1 T2 61 T4 44 T6 1275
valid_sources[0x09] 428454 1 T2 87 T4 109 T6 1363
valid_sources[0x0a] 1011066 1 T2 81 T4 68 T6 1514
valid_sources[0x0b] 435689 1 T2 80 T4 74 T6 1313
valid_sources[0x0c] 426905 1 T2 97 T4 99 T6 1343
valid_sources[0x0d] 423208 1 T2 74 T4 60 T6 1306
valid_sources[0x0e] 429131 1 T2 131 T4 35 T6 1356
valid_sources[0x0f] 425027 1 T2 85 T4 79 T6 1338
valid_sources[0x10] 1565388 1 T2 77 T4 93 T6 1341
valid_sources[0x11] 426332 1 T2 86 T4 82 T6 1378
valid_sources[0x12] 424280 1 T2 75 T4 72 T6 1533
valid_sources[0x13] 426917 1 T2 70 T4 44 T6 1486
valid_sources[0x14] 779641 1 T2 46 T4 73 T6 1423
valid_sources[0x15] 428862 1 T2 74 T4 64 T6 1255
valid_sources[0x16] 426350 1 T2 95 T4 51 T6 1307
valid_sources[0x17] 427110 1 T2 76 T4 71 T6 1410
valid_sources[0x18] 427476 1 T2 82 T4 84 T6 1261
valid_sources[0x19] 426175 1 T2 78 T4 53 T6 1382
valid_sources[0x1a] 429764 1 T2 73 T4 72 T6 1321
valid_sources[0x1b] 425568 1 T2 98 T4 89 T6 1386
valid_sources[0x1c] 427713 1 T2 64 T4 104 T6 1282
valid_sources[0x1d] 952087 1 T2 88 T4 89 T6 1501
valid_sources[0x1e] 427575 1 T2 34 T4 66 T6 1277
valid_sources[0x1f] 581327 1 T2 51 T4 60 T6 1274
valid_sources[0x20] 429651 1 T2 85 T4 111 T6 1393
valid_sources[0x21] 428511 1 T2 90 T4 77 T6 1374
valid_sources[0x22] 429254 1 T2 67 T4 48 T6 1304
valid_sources[0x23] 426465 1 T2 71 T4 97 T6 1345
valid_sources[0x24] 426003 1 T2 59 T4 73 T6 1366
valid_sources[0x25] 430040 1 T2 79 T4 72 T6 1466
valid_sources[0x26] 426126 1 T2 53 T4 54 T6 1344
valid_sources[0x27] 541529 1 T2 71 T4 56 T6 1333
valid_sources[0x28] 428438 1 T2 97 T4 58 T6 1428
valid_sources[0x29] 430072 1 T2 71 T4 76 T6 1364
valid_sources[0x2a] 427070 1 T2 103 T4 71 T6 1541
valid_sources[0x2b] 427375 1 T2 61 T4 61 T6 1413
valid_sources[0x2c] 430532 1 T2 60 T4 76 T6 1267
valid_sources[0x2d] 427912 1 T2 105 T4 67 T6 1500
valid_sources[0x2e] 424639 1 T2 56 T4 73 T6 1376
valid_sources[0x2f] 428999 1 T2 72 T4 80 T6 1501
valid_sources[0x30] 426255 1 T2 78 T4 84 T6 1315
valid_sources[0x31] 426910 1 T2 46 T4 80 T6 1441
valid_sources[0x32] 427410 1 T2 50 T4 105 T6 1351
valid_sources[0x33] 431726 1 T2 92 T4 46 T6 1283
valid_sources[0x34] 719105 1 T2 66 T4 73 T6 1432
valid_sources[0x35] 430329 1 T2 74 T4 63 T6 1303
valid_sources[0x36] 426820 1 T2 115 T4 74 T6 1459
valid_sources[0x37] 424437 1 T2 84 T4 101 T6 1337
valid_sources[0x38] 427299 1 T2 84 T4 95 T6 1428
valid_sources[0x39] 426117 1 T2 42 T4 50 T6 1342
valid_sources[0x3a] 429220 1 T2 80 T4 64 T6 1351
valid_sources[0x3b] 441839 1 T2 80 T4 74 T6 1449
valid_sources[0x3c] 423626 1 T2 55 T4 83 T6 1358
valid_sources[0x3d] 428753 1 T2 95 T4 52 T6 1406
valid_sources[0x3e] 429799 1 T2 91 T4 75 T6 1267
valid_sources[0x3f] 424743 1 T2 81 T4 84 T6 1235
valid_sources[0x40] 434171 1 T2 92 T4 50 T6 1399
valid_sources[0x41] 429051 1 T2 78 T4 48 T6 1358
valid_sources[0x42] 428485 1 T2 117 T4 94 T6 1465
valid_sources[0x43] 429234 1 T2 91 T4 76 T6 1411
valid_sources[0x44] 426317 1 T2 96 T4 80 T6 1313
valid_sources[0x45] 424799 1 T2 65 T4 74 T6 1459
valid_sources[0x46] 423695 1 T2 64 T4 54 T6 1348
valid_sources[0x47] 424193 1 T2 64 T4 65 T6 1424
valid_sources[0x48] 429854 1 T2 64 T4 74 T6 1359
valid_sources[0x49] 426217 1 T2 55 T4 70 T6 1380
valid_sources[0x4a] 476799 1 T2 78 T4 81 T6 1441
valid_sources[0x4b] 427403 1 T2 42 T4 46 T6 1392
valid_sources[0x4c] 523303 1 T2 44 T4 77 T6 1405
valid_sources[0x4d] 479976 1 T2 76 T4 87 T6 1458
valid_sources[0x4e] 424875 1 T2 66 T4 71 T6 1507
valid_sources[0x4f] 458474 1 T2 79 T4 91 T6 1361
valid_sources[0x50] 427011 1 T2 84 T4 62 T6 1308
valid_sources[0x51] 426596 1 T2 85 T4 99 T6 1384
valid_sources[0x52] 776679 1 T2 63 T3 27470 T4 95
valid_sources[0x53] 426162 1 T2 57 T4 58 T6 1421
valid_sources[0x54] 425935 1 T2 45 T4 81 T6 1299
valid_sources[0x55] 427537 1 T2 70 T4 68 T6 1474
valid_sources[0x56] 2926267 1 T2 65 T4 60 T6 1458
valid_sources[0x57] 632929 1 T2 67 T4 86 T6 1547
valid_sources[0x58] 966444 1 T2 81 T4 99 T6 1419
valid_sources[0x59] 1591592 1 T2 101 T4 47 T6 1383
valid_sources[0x5a] 424905 1 T2 52 T4 72 T6 1325
valid_sources[0x5b] 425057 1 T2 95 T4 49 T6 1323
valid_sources[0x5c] 425387 1 T2 68 T4 97 T6 1348
valid_sources[0x5d] 425718 1 T2 96 T4 87 T6 1420
valid_sources[0x5e] 426417 1 T2 98 T4 79 T6 1350
valid_sources[0x5f] 427584 1 T2 48 T4 97 T6 1440
valid_sources[0x60] 428694 1 T2 85 T4 82 T6 1274
valid_sources[0x61] 439303 1 T2 72 T4 69 T6 1392
valid_sources[0x62] 427005 1 T2 80 T4 42 T6 1378
valid_sources[0x63] 433456 1 T2 72 T4 97 T6 1441
valid_sources[0x64] 424370 1 T2 36 T4 62 T6 1419
valid_sources[0x65] 425271 1 T2 117 T4 48 T6 1394
valid_sources[0x66] 425649 1 T2 87 T4 102 T6 1313
valid_sources[0x67] 425319 1 T2 93 T4 58 T6 1355
valid_sources[0x68] 474050 1 T2 111 T4 94 T6 1428
valid_sources[0x69] 428436 1 T2 91 T4 56 T6 1435
valid_sources[0x6a] 605944 1 T2 51 T4 75 T6 1451
valid_sources[0x6b] 426099 1 T2 68 T4 88 T6 1375
valid_sources[0x6c] 438581 1 T2 83 T4 67 T5 8968
valid_sources[0x6d] 427038 1 T2 68 T4 91 T6 1399
valid_sources[0x6e] 429124 1 T2 70 T4 82 T6 1487
valid_sources[0x6f] 434093 1 T2 94 T4 54 T6 1401
valid_sources[0x70] 1130132 1 T2 46 T4 87 T6 1358
valid_sources[0x71] 441402 1 T2 95 T4 59 T6 1270
valid_sources[0x72] 426914 1 T2 63 T4 70 T6 1381
valid_sources[0x73] 427541 1 T2 76 T4 129 T6 1447
valid_sources[0x74] 428241 1 T2 93 T4 67 T6 1363
valid_sources[0x75] 1365781 1 T2 84 T4 122 T6 1242
valid_sources[0x76] 424538 1 T2 80 T4 65 T6 1348
valid_sources[0x77] 1909035 1 T2 61 T4 64 T6 1395
valid_sources[0x78] 428188 1 T2 56 T4 109 T6 1303
valid_sources[0x79] 428888 1 T2 85 T4 78 T6 1216
valid_sources[0x7a] 767111 1 T2 96 T4 62 T6 1433
valid_sources[0x7b] 426464 1 T2 76 T4 71 T6 1269
valid_sources[0x7c] 426614 1 T2 84 T4 86 T6 1344
valid_sources[0x7d] 426755 1 T2 91 T4 68 T6 1319
valid_sources[0x7e] 1065374 1 T2 72 T4 86 T6 1334
valid_sources[0x7f] 424654 1 T2 65 T4 72 T6 1366
valid_sources[0x80] 425683 1 T2 94 T4 56 T6 1366



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 68309234 1 T1 56 T2 9902 T3 13564
values[0x0] all_enables biggest_size 615058 1 T1 22 T2 12 T3 34
values[0x1] all_enables biggest_size 612975 1 T1 6 T2 11 T3 22

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%