SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_timer_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 140827437 | 0 | T1 | 197 | T2 | 19797 | T3 | 27470 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 140827197 | 1 | T1 | 197 | T2 | 19797 | T3 | 27470 | |||
values[1] | 17 | 1 | T28 | 2 | T29 | 2 | T30 | 1 | |||
values[2] | 7 | 1 | T28 | 2 | T106 | 4 | T107 | 1 | |||
values[3] | 119 | 1 | T28 | 7 | T29 | 13 | T30 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 140827175 | 1 | T1 | 197 | T2 | 19797 | T3 | 27470 | |||
values[1] | 33 | 1 | T28 | 1 | T29 | 2 | T108 | 5 | |||
values[2] | 8 | 1 | T28 | 1 | T29 | 2 | T108 | 1 | |||
values[3] | 127 | 1 | T28 | 8 | T29 | 9 | T30 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 140827067 | 1 | T1 | 197 | T2 | 19797 | T3 | 27470 | |||
auto[TlIntgErrCmd] | 108 | 1 | T28 | 5 | T29 | 9 | T30 | 3 | |||
auto[TlIntgErrData] | 130 | 1 | T28 | 6 | T29 | 6 | T30 | 5 | |||
auto[TlIntgErrBoth] | 132 | 1 | T28 | 9 | T29 | 15 | T30 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |