Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2149774	0	0
cfg0_rd_A	2147483647	6699	0	0
compare_lower0_0_rd_A	2147483647	7191	0	0
compare_upper0_0_rd_A	2147483647	6434	0	0
ctrl_rd_A	2147483647	6310	0	0
intr_enable0_rd_A	2147483647	8035	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2149774	0	0
T11	230812	7530	0	0
T12	0	497223	0	0
T13	0	57107	0	0
T34	0	215736	0	0
T35	0	53341	0	0
T36	0	308740	0	0
T37	0	178372	0	0
T38	0	268586	0	0
T39	0	93279	0	0
T40	0	49011	0	0
T41	125671	0	0	0
T42	102584	0	0	0
T43	123072	0	0	0
T44	420016	0	0	0
T45	496238	0	0	0
T46	105259	0	0	0
T47	859006	0	0	0
T48	817699	0	0	0
T49	312782	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6699	0	0
T13	202154	312	0	0
T31	0	33	0	0
T32	0	14	0	0
T38	0	2896	0	0
T50	0	263	0	0
T51	0	264	0	0
T52	0	34	0	0
T53	0	1	0	0
T54	0	246	0	0
T55	0	53	0	0
T56	694350	0	0	0
T57	860564	0	0	0
T58	233450	0	0	0
T59	411442	0	0	0
T60	452370	0	0	0
T61	403422	0	0	0
T62	210730	0	0	0
T63	478079	0	0	0
T64	415486	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7191	0	0
T13	202154	315	0	0
T31	0	16	0	0
T32	0	56	0	0
T38	0	3244	0	0
T50	0	327	0	0
T51	0	320	0	0
T52	0	3	0	0
T53	0	9	0	0
T54	0	212	0	0
T55	0	46	0	0
T56	694350	0	0	0
T57	860564	0	0	0
T58	233450	0	0	0
T59	411442	0	0	0
T60	452370	0	0	0
T61	403422	0	0	0
T62	210730	0	0	0
T63	478079	0	0	0
T64	415486	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6434	0	0
T13	202154	343	0	0
T31	0	4	0	0
T32	0	37	0	0
T38	0	2613	0	0
T50	0	273	0	0
T51	0	292	0	0
T52	0	19	0	0
T53	0	14	0	0
T54	0	220	0	0
T55	0	48	0	0
T56	694350	0	0	0
T57	860564	0	0	0
T58	233450	0	0	0
T59	411442	0	0	0
T60	452370	0	0	0
T61	403422	0	0	0
T62	210730	0	0	0
T63	478079	0	0	0
T64	415486	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6310	0	0
T13	202154	257	0	0
T31	0	23	0	0
T32	0	42	0	0
T38	0	2657	0	0
T50	0	207	0	0
T51	0	322	0	0
T52	0	12	0	0
T53	0	16	0	0
T54	0	195	0	0
T56	694350	0	0	0
T57	860564	0	0	0
T58	233450	0	0	0
T59	411442	0	0	0
T60	452370	0	0	0
T61	403422	0	0	0
T62	210730	0	0	0
T63	478079	0	0	0
T64	415486	0	0	0
T65	0	7	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8035	0	0
T9	579351	32	0	0
T10	737239	0	0	0
T13	0	477	0	0
T33	236373	8	0	0
T49	0	9	0	0
T66	580683	148	0	0
T67	0	32	0	0
T68	0	24	0	0
T69	0	53	0	0
T70	0	6	0	0
T71	0	48	0	0
T72	917565	0	0	0
T73	149973	0	0	0
T74	296157	0	0	0
T75	495526	0	0	0
T76	398154	0	0	0
T77	712720	0	0	0