Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65624421	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	66542005	1		T1	1123		T2	121242		T3	3647

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	131361495	1		T1	2188		T2	242601		T3	7192
values[0x0]	382697	1		T1	7		T2	23		T3	20
values[0x1]	422234	1		T1	7		T2	27		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52423716	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	79742710	1		T1	1334		T2	145683		T3	4367

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	407072	1		T3	20		T4	197		T5	97
valid_sources[0x01]	436809	1		T3	27		T4	208		T5	65
valid_sources[0x02]	402448	1		T3	36		T4	198		T5	65
valid_sources[0x03]	403500	1		T1	54		T3	39		T4	208
valid_sources[0x04]	408476	1		T3	33		T4	187		T5	77
valid_sources[0x05]	689395	1		T3	35		T4	195		T5	53
valid_sources[0x06]	425146	1		T3	21		T4	187		T5	52
valid_sources[0x07]	406779	1		T1	26		T3	32		T4	198
valid_sources[0x08]	405544	1		T3	29		T4	213		T5	35
valid_sources[0x09]	406500	1		T1	5		T3	24		T4	210
valid_sources[0x0a]	1194234	1		T3	25		T4	219		T5	52
valid_sources[0x0b]	405732	1		T3	24		T4	199		T5	55
valid_sources[0x0c]	473008	1		T3	42		T4	219		T5	60
valid_sources[0x0d]	1145574	1		T3	18		T4	226		T5	47
valid_sources[0x0e]	407329	1		T1	12		T3	26		T4	225
valid_sources[0x0f]	404741	1		T3	26		T4	193		T5	40
valid_sources[0x10]	526103	1		T3	40		T4	196		T5	57
valid_sources[0x11]	460274	1		T1	12		T3	35		T4	210
valid_sources[0x12]	409061	1		T1	2		T3	31		T4	194
valid_sources[0x13]	407990	1		T3	28		T4	209		T5	71
valid_sources[0x14]	407435	1		T3	24		T4	211		T5	81
valid_sources[0x15]	1178503	1		T1	11		T3	34		T4	206
valid_sources[0x16]	466115	1		T3	29		T4	213		T5	62
valid_sources[0x17]	407721	1		T3	32		T4	199		T5	71
valid_sources[0x18]	408016	1		T3	33		T4	196		T5	63
valid_sources[0x19]	497378	1		T1	4		T3	21		T4	227
valid_sources[0x1a]	409185	1		T1	66		T3	22		T4	197
valid_sources[0x1b]	407069	1		T3	21		T4	207		T5	94
valid_sources[0x1c]	462152	1		T3	24		T4	206		T5	67
valid_sources[0x1d]	406014	1		T3	30		T4	203		T5	65
valid_sources[0x1e]	631583	1		T3	40		T4	192		T5	55
valid_sources[0x1f]	403674	1		T1	14		T3	30		T4	188
valid_sources[0x20]	420012	1		T1	32		T3	38		T4	235
valid_sources[0x21]	407898	1		T1	3		T3	33		T4	199
valid_sources[0x22]	407302	1		T3	40		T4	195		T5	93
valid_sources[0x23]	406055	1		T3	27		T4	204		T5	58
valid_sources[0x24]	407227	1		T1	10		T3	28		T4	203
valid_sources[0x25]	406392	1		T1	5		T3	28		T4	219
valid_sources[0x26]	408854	1		T3	26		T4	207		T5	82
valid_sources[0x27]	404168	1		T3	24		T4	230		T5	73
valid_sources[0x28]	449721	1		T1	2		T3	41		T4	199
valid_sources[0x29]	402500	1		T3	16		T4	210		T5	99
valid_sources[0x2a]	406257	1		T1	10		T3	31		T4	222
valid_sources[0x2b]	406738	1		T3	36		T4	210		T5	84
valid_sources[0x2c]	418022	1		T3	18		T4	215		T5	57
valid_sources[0x2d]	405815	1		T1	15		T3	38		T4	215
valid_sources[0x2e]	408880	1		T3	16		T4	206		T5	58
valid_sources[0x2f]	1630313	1		T3	18		T4	212		T5	51
valid_sources[0x30]	416001	1		T3	26		T4	204		T5	51
valid_sources[0x31]	1021951	1		T1	61		T3	31		T4	203
valid_sources[0x32]	407087	1		T3	16		T4	195		T5	52
valid_sources[0x33]	407127	1		T3	21		T4	213		T5	68
valid_sources[0x34]	404044	1		T3	39		T4	230		T5	84
valid_sources[0x35]	1308854	1		T3	28		T4	235		T5	58
valid_sources[0x36]	404616	1		T3	21		T4	198		T5	62
valid_sources[0x37]	404796	1		T3	23		T4	198		T5	82
valid_sources[0x38]	403684	1		T3	26		T4	213		T5	79
valid_sources[0x39]	417397	1		T1	7		T3	25		T4	200
valid_sources[0x3a]	406488	1		T1	12		T3	30		T4	241
valid_sources[0x3b]	407033	1		T1	12		T3	28		T4	201
valid_sources[0x3c]	405257	1		T3	34		T4	211		T5	71
valid_sources[0x3d]	404515	1		T3	40		T4	241		T5	65
valid_sources[0x3e]	427899	1		T1	10		T3	20		T4	170
valid_sources[0x3f]	403994	1		T3	22		T4	219		T5	46
valid_sources[0x40]	406236	1		T3	22		T4	222		T5	43
valid_sources[0x41]	480515	1		T3	34		T4	207		T5	59
valid_sources[0x42]	404669	1		T3	35		T4	190		T5	41
valid_sources[0x43]	405313	1		T3	34		T4	198		T5	33
valid_sources[0x44]	859688	1		T3	23		T4	208		T5	40
valid_sources[0x45]	404735	1		T3	21		T4	216		T5	62
valid_sources[0x46]	406169	1		T1	2		T3	21		T4	228
valid_sources[0x47]	1104546	1		T3	29		T4	221		T5	46
valid_sources[0x48]	1199952	1		T1	2		T3	27		T4	191
valid_sources[0x49]	406196	1		T3	22		T4	213		T5	69
valid_sources[0x4a]	4427026	1		T1	22		T3	29		T4	188
valid_sources[0x4b]	406811	1		T3	31		T4	200		T5	60
valid_sources[0x4c]	2184283	1		T1	1		T3	26		T4	263
valid_sources[0x4d]	407778	1		T1	40		T3	27		T4	224
valid_sources[0x4e]	406913	1		T3	33		T4	192		T5	56
valid_sources[0x4f]	408665	1		T1	20		T3	23		T4	246
valid_sources[0x50]	410412	1		T3	33		T4	195		T5	62
valid_sources[0x51]	439433	1		T1	20		T3	28		T4	223
valid_sources[0x52]	408086	1		T3	30		T4	202		T5	46
valid_sources[0x53]	405198	1		T1	18		T3	28		T4	198
valid_sources[0x54]	404004	1		T3	16		T4	230		T5	89
valid_sources[0x55]	909588	1		T3	34		T4	219		T5	64
valid_sources[0x56]	406852	1		T1	29		T3	27		T4	228
valid_sources[0x57]	437573	1		T3	18		T4	179		T5	63
valid_sources[0x58]	406766	1		T1	20		T3	32		T4	190
valid_sources[0x59]	405815	1		T3	38		T4	180		T5	70
valid_sources[0x5a]	405122	1		T3	30		T4	203		T5	53
valid_sources[0x5b]	410973	1		T3	36		T4	233		T5	53
valid_sources[0x5c]	441434	1		T1	43		T3	22		T4	197
valid_sources[0x5d]	1113553	1		T3	29		T4	197		T5	76
valid_sources[0x5e]	747506	1		T3	25		T4	212		T5	56
valid_sources[0x5f]	403725	1		T3	19		T4	180		T5	60
valid_sources[0x60]	409453	1		T3	26		T4	231		T5	60
valid_sources[0x61]	979460	1		T3	17		T4	192		T5	63
valid_sources[0x62]	403687	1		T3	35		T4	222		T5	82
valid_sources[0x63]	404082	1		T3	32		T4	198		T5	49
valid_sources[0x64]	475707	1		T3	25		T4	221		T5	42
valid_sources[0x65]	407064	1		T1	61		T3	23		T4	228
valid_sources[0x66]	404795	1		T1	32		T3	26		T4	207
valid_sources[0x67]	404155	1		T3	16		T4	202		T5	55
valid_sources[0x68]	403110	1		T3	33		T4	211		T5	80
valid_sources[0x69]	403322	1		T3	22		T4	189		T5	57
valid_sources[0x6a]	407690	1		T3	37		T4	194		T5	87
valid_sources[0x6b]	1600215	1		T3	27		T4	208		T5	37
valid_sources[0x6c]	1270407	1		T3	24		T4	198		T5	49
valid_sources[0x6d]	404476	1		T3	23		T4	220		T5	60
valid_sources[0x6e]	405951	1		T3	37		T4	211		T5	54
valid_sources[0x6f]	408812	1		T3	26		T4	204		T5	44
valid_sources[0x70]	406079	1		T3	29		T4	216		T5	48
valid_sources[0x71]	401300	1		T3	29		T4	216		T5	69
valid_sources[0x72]	410509	1		T1	29		T3	23		T4	183
valid_sources[0x73]	402993	1		T3	29		T4	209		T5	60
valid_sources[0x74]	405464	1		T3	27		T4	200		T5	67
valid_sources[0x75]	404269	1		T3	31		T4	208		T5	55
valid_sources[0x76]	407136	1		T1	22		T3	32		T4	195
valid_sources[0x77]	404362	1		T1	19		T3	21		T4	211
valid_sources[0x78]	431531	1		T1	12		T3	33		T4	195
valid_sources[0x79]	400768	1		T3	34		T4	192		T5	36
valid_sources[0x7a]	407631	1		T1	47		T3	23		T4	188
valid_sources[0x7b]	406901	1		T3	29		T4	189		T5	47
valid_sources[0x7c]	406943	1		T3	21		T4	202		T5	63
valid_sources[0x7d]	409189	1		T3	24		T4	219		T5	59
valid_sources[0x7e]	429622	1		T3	33		T4	204		T5	71
valid_sources[0x7f]	405874	1		T3	21		T4	212		T5	66
valid_sources[0x80]	405442	1		T3	30		T4	208		T5	59

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65795329

1

T1

1113

T2

121206

T3

3614

values[0x0]

all_enables

biggest_size

373826

1

T1

6

T2

17

T3

17

values[0x1]

all_enables

biggest_size

372850

1

T1

4

T2

19

T3

16