Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1292983	0	0
cfg0_rd_A	2147483647	1933	0	0
compare_lower0_0_rd_A	2147483647	1817	0	0
compare_upper0_0_rd_A	2147483647	1777	0	0
ctrl_rd_A	2147483647	1677	0	0
intr_enable0_rd_A	2147483647	2830	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1292983	0	0
T12	122593	394944	0	0
T13	0	95758	0	0
T14	0	72708	0	0
T21	722771	0	0	0
T22	527430	0	0	0
T23	823695	0	0	0
T24	557157	0	0	0
T25	222921	0	0	0
T26	749410	0	0	0
T27	995583	0	0	0
T28	0	12	0	0
T35	0	127058	0	0
T36	0	131532	0	0
T37	0	32115	0	0
T38	0	185746	0	0
T39	0	93646	0	0
T40	0	145415	0	0
T41	183786	0	0	0
T42	197714	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1933	0	0
T13	329531	517	0	0
T37	0	340	0	0
T43	0	9	0	0
T44	0	46	0	0
T45	0	5	0	0
T46	0	9	0	0
T47	0	171	0	0
T48	0	17	0	0
T49	0	15	0	0
T50	0	33	0	0
T51	467913	0	0	0
T52	157510	0	0	0
T53	4484	0	0	0
T54	10015	0	0	0
T55	546755	0	0	0
T56	590657	0	0	0
T57	102212	0	0	0
T58	957637	0	0	0
T59	273841	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1817	0	0
T13	329531	536	0	0
T37	0	472	0	0
T43	0	8	0	0
T44	0	13	0	0
T47	0	119	0	0
T48	0	11	0	0
T49	0	6	0	0
T50	0	98	0	0
T51	467913	0	0	0
T52	157510	0	0	0
T53	4484	0	0	0
T54	10015	0	0	0
T55	546755	0	0	0
T56	590657	0	0	0
T57	102212	0	0	0
T58	957637	0	0	0
T59	273841	0	0	0
T60	0	92	0	0
T61	0	23	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1777	0	0
T13	329531	562	0	0
T37	0	344	0	0
T43	0	12	0	0
T44	0	40	0	0
T46	0	7	0	0
T47	0	104	0	0
T48	0	7	0	0
T49	0	12	0	0
T50	0	61	0	0
T51	467913	0	0	0
T52	157510	0	0	0
T53	4484	0	0	0
T54	10015	0	0	0
T55	546755	0	0	0
T56	590657	0	0	0
T57	102212	0	0	0
T58	957637	0	0	0
T59	273841	0	0	0
T60	0	84	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1677	0	0
T13	329531	503	0	0
T37	0	362	0	0
T43	0	6	0	0
T44	0	8	0	0
T46	0	2	0	0
T47	0	112	0	0
T48	0	18	0	0
T49	0	9	0	0
T50	0	53	0	0
T51	467913	0	0	0
T52	157510	0	0	0
T53	4484	0	0	0
T54	10015	0	0	0
T55	546755	0	0	0
T56	590657	0	0	0
T57	102212	0	0	0
T58	957637	0	0	0
T59	273841	0	0	0
T62	0	1	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2830	0	0
T13	0	698	0	0
T63	516829	47	0	0
T64	447604	22	0	0
T65	0	42	0	0
T66	0	94	0	0
T67	0	38	0	0
T68	0	62	0	0
T69	0	54	0	0
T70	0	24	0	0
T71	0	26	0	0
T72	186786	0	0	0
T73	317856	0	0	0
T74	781161	0	0	0
T75	915930	0	0	0
T76	404608	0	0	0
T77	157780	0	0	0
T78	11123	0	0	0
T79	700710	0	0	0