Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1658199	0	0
cfg0_rd_A	2147483647	5161	0	0
compare_lower0_0_rd_A	2147483647	5819	0	0
compare_upper0_0_rd_A	2147483647	5355	0	0
ctrl_rd_A	2147483647	5398	0	0
intr_enable0_rd_A	2147483647	7460	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1658199	0	0
T12	119454	229152	0	0
T13	777724	133355	0	0
T14	475276	63879	0	0
T23	432214	0	0	0
T24	895325	0	0	0
T25	120085	0	0	0
T30	381920	117617	0	0
T31	0	84908	0	0
T32	0	54462	0	0
T33	0	45247	0	0
T34	0	52391	0	0
T35	0	245465	0	0
T36	0	40827	0	0
T37	420909	0	0	0
T38	422604	0	0	0
T39	321908	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5161	0	0
T12	119454	2148	0	0
T13	777724	752	0	0
T14	475276	0	0	0
T23	432214	0	0	0
T24	895325	0	0	0
T25	120085	0	0	0
T30	381920	0	0	0
T31	0	699	0	0
T37	420909	0	0	0
T38	422604	0	0	0
T39	321908	0	0	0
T40	0	626	0	0
T41	0	35	0	0
T42	0	19	0	0
T43	0	23	0	0
T44	0	52	0	0
T45	0	188	0	0
T46	0	8	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5819	0	0
T12	119454	2516	0	0
T13	777724	770	0	0
T14	475276	0	0	0
T23	432214	0	0	0
T24	895325	0	0	0
T25	120085	0	0	0
T30	381920	0	0	0
T31	0	937	0	0
T37	420909	0	0	0
T38	422604	0	0	0
T39	321908	0	0	0
T40	0	835	0	0
T41	0	18	0	0
T42	0	9	0	0
T43	0	26	0	0
T44	0	37	0	0
T45	0	237	0	0
T46	0	9	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5355	0	0
T12	119454	2558	0	0
T13	777724	726	0	0
T14	475276	0	0	0
T23	432214	0	0	0
T24	895325	0	0	0
T25	120085	0	0	0
T30	381920	0	0	0
T31	0	731	0	0
T37	420909	0	0	0
T38	422604	0	0	0
T39	321908	0	0	0
T40	0	648	0	0
T41	0	9	0	0
T42	0	11	0	0
T43	0	19	0	0
T44	0	28	0	0
T45	0	227	0	0
T47	0	40	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5398	0	0
T12	119454	2444	0	0
T13	777724	608	0	0
T14	475276	0	0	0
T23	432214	0	0	0
T24	895325	0	0	0
T25	120085	0	0	0
T30	381920	0	0	0
T31	0	917	0	0
T37	420909	0	0	0
T38	422604	0	0	0
T39	321908	0	0	0
T40	0	697	0	0
T41	0	20	0	0
T42	0	18	0	0
T43	0	14	0	0
T44	0	39	0	0
T45	0	221	0	0
T48	0	7	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7460	0	0
T12	119454	2892	0	0
T13	777724	1068	0	0
T14	475276	0	0	0
T23	432214	78	0	0
T24	895325	0	0	0
T25	120085	0	0	0
T30	381920	0	0	0
T31	0	1018	0	0
T37	420909	0	0	0
T38	422604	0	0	0
T39	321908	0	0	0
T49	0	34	0	0
T50	0	10	0	0
T51	0	14	0	0
T52	0	162	0	0
T53	0	5	0	0
T54	0	29	0	0