Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1994013	0	0
cfg0_rd_A	2147483647	4986	0	0
compare_lower0_0_rd_A	2147483647	5030	0	0
compare_upper0_0_rd_A	2147483647	4563	0	0
ctrl_rd_A	2147483647	4658	0	0
intr_enable0_rd_A	2147483647	6102	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1994013	0	0
T6	482085	147324	0	0
T7	185685	0	0	0
T8	207781	0	0	0
T9	133125	0	0	0
T10	163127	0	0	0
T11	0	42441	0	0
T12	0	83554	0	0
T33	0	255935	0	0
T34	0	190858	0	0
T35	0	237698	0	0
T36	0	261959	0	0
T37	0	131412	0	0
T38	0	26976	0	0
T39	0	143732	0	0
T40	378483	0	0	0
T41	764124	0	0	0
T42	134031	0	0	0
T43	15679	0	0	0
T44	659130	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4986	0	0
T28	0	33	0	0
T45	134444	351	0	0
T46	0	2725	0	0
T47	0	242	0	0
T48	0	25	0	0
T49	0	72	0	0
T50	0	18	0	0
T51	0	6	0	0
T52	0	1	0	0
T53	0	221	0	0
T54	303145	0	0	0
T55	594237	0	0	0
T56	498754	0	0	0
T57	10123	0	0	0
T58	174402	0	0	0
T59	122436	0	0	0
T60	318942	0	0	0
T61	498244	0	0	0
T62	120139	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5030	0	0
T28	0	27	0	0
T45	134444	363	0	0
T46	0	2913	0	0
T47	0	322	0	0
T48	0	3	0	0
T49	0	53	0	0
T50	0	6	0	0
T51	0	9	0	0
T54	303145	0	0	0
T55	594237	0	0	0
T56	498754	0	0	0
T57	10123	0	0	0
T58	174402	0	0	0
T59	122436	0	0	0
T60	318942	0	0	0
T61	498244	0	0	0
T62	120139	0	0	0
T63	0	7	0	0
T64	0	11	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4563	0	0
T28	0	12	0	0
T45	134444	283	0	0
T46	0	2622	0	0
T47	0	236	0	0
T48	0	3	0	0
T49	0	38	0	0
T50	0	11	0	0
T51	0	9	0	0
T54	303145	0	0	0
T55	594237	0	0	0
T56	498754	0	0	0
T57	10123	0	0	0
T58	174402	0	0	0
T59	122436	0	0	0
T60	318942	0	0	0
T61	498244	0	0	0
T62	120139	0	0	0
T63	0	14	0	0
T64	0	9	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4658	0	0
T28	0	2	0	0
T45	134444	399	0	0
T46	0	2661	0	0
T47	0	299	0	0
T48	0	22	0	0
T49	0	35	0	0
T50	0	14	0	0
T51	0	4	0	0
T52	0	4	0	0
T54	303145	0	0	0
T55	594237	0	0	0
T56	498754	0	0	0
T57	10123	0	0	0
T58	174402	0	0	0
T59	122436	0	0	0
T60	318942	0	0	0
T61	498244	0	0	0
T62	120139	0	0	0
T64	0	4	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6102	0	0
T34	825403	0	0	0
T45	0	502	0	0
T46	0	2949	0	0
T47	0	357	0	0
T65	152545	38	0	0
T66	0	21	0	0
T67	0	22	0	0
T68	0	21	0	0
T69	0	52	0	0
T70	0	65	0	0
T71	0	73	0	0
T72	221467	0	0	0
T73	365906	0	0	0
T74	182863	0	0	0
T75	308261	0	0	0
T76	141284	0	0	0
T77	142566	0	0	0
T78	458554	0	0	0
T79	134000	0	0	0