Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1110803	0	0
cfg0_rd_A	2147483647	4382	0	0
compare_lower0_0_rd_A	2147483647	4387	0	0
compare_upper0_0_rd_A	2147483647	3839	0	0
ctrl_rd_A	2147483647	4017	0	0
intr_enable0_rd_A	2147483647	4967	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1110803	0	0
T1	940637	42338	0	0
T2	123284	0	0	0
T3	130976	0	0	0
T4	9447	0	0	0
T5	106100	0	0	0
T6	7642	0	0	0
T7	371510	0	0	0
T8	380918	0	0	0
T9	577762	0	0	0
T10	842246	0	0	0
T11	0	60042	0	0
T12	0	56776	0	0
T27	0	152345	0	0
T28	0	39612	0	0
T29	0	221692	0	0
T30	0	34056	0	0
T31	0	60901	0	0
T32	0	165113	0	0
T33	0	168398	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4382	0	0
T22	0	211	0	0
T24	0	95	0	0
T28	158078	433	0	0
T32	0	1662	0	0
T34	0	12	0	0
T35	0	671	0	0
T36	0	15	0	0
T37	0	47	0	0
T38	0	2	0	0
T39	0	19	0	0
T40	820680	0	0	0
T41	225226	0	0	0
T42	445956	0	0	0
T43	118636	0	0	0
T44	221361	0	0	0
T45	150528	0	0	0
T46	4590	0	0	0
T47	444764	0	0	0
T48	271712	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4387	0	0
T22	0	120	0	0
T24	0	57	0	0
T28	158078	456	0	0
T32	0	2033	0	0
T34	0	13	0	0
T35	0	638	0	0
T36	0	20	0	0
T37	0	14	0	0
T38	0	1	0	0
T39	0	12	0	0
T40	820680	0	0	0
T41	225226	0	0	0
T42	445956	0	0	0
T43	118636	0	0	0
T44	221361	0	0	0
T45	150528	0	0	0
T46	4590	0	0	0
T47	444764	0	0	0
T48	271712	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3839	0	0
T22	0	110	0	0
T24	0	51	0	0
T28	158078	360	0	0
T32	0	1643	0	0
T34	0	5	0	0
T35	0	630	0	0
T36	0	12	0	0
T37	0	16	0	0
T38	0	8	0	0
T39	0	22	0	0
T40	820680	0	0	0
T41	225226	0	0	0
T42	445956	0	0	0
T43	118636	0	0	0
T44	221361	0	0	0
T45	150528	0	0	0
T46	4590	0	0	0
T47	444764	0	0	0
T48	271712	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4017	0	0
T22	0	137	0	0
T24	0	49	0	0
T28	158078	425	0	0
T32	0	1676	0	0
T34	0	21	0	0
T35	0	659	0	0
T36	0	20	0	0
T37	0	7	0	0
T39	0	16	0	0
T40	820680	0	0	0
T41	225226	0	0	0
T42	445956	0	0	0
T43	118636	0	0	0
T44	221361	0	0	0
T45	150528	0	0	0
T46	4590	0	0	0
T47	444764	0	0	0
T48	271712	0	0	0
T49	0	7	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4967	0	0
T28	0	400	0	0
T50	303929	59	0	0
T51	486864	6	0	0
T52	1755	6	0	0
T53	0	101	0	0
T54	0	8	0	0
T55	0	19	0	0
T56	0	41	0	0
T57	0	18	0	0
T58	0	38	0	0
T59	257103	0	0	0
T60	180216	0	0	0
T61	154576	0	0	0
T62	576174	0	0	0
T63	108623	0	0	0
T64	417512	0	0	0
T65	114179	0	0	0