Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	63868593	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	65393330	1		T1	9063		T2	247459		T3	20733

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	127944705	1		T1	17918		T2	494774		T3	41405
values[0x0]	627385	1		T1	44		T2	24		T3	15
values[0x1]	689833	1		T1	34		T2	26		T3	35

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51003610	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	78258313	1		T1	10846		T2	297154		T3	24999

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	389883	1		T1	68		T2	1917		T5	38
valid_sources[0x01]	388479	1		T1	61		T2	1920		T5	55
valid_sources[0x02]	389929	1		T1	78		T2	1914		T5	50
valid_sources[0x03]	653837	1		T1	97		T2	1891		T5	61
valid_sources[0x04]	1024009	1		T1	51		T2	1923		T5	69
valid_sources[0x05]	393166	1		T1	68		T2	1894		T5	57
valid_sources[0x06]	386948	1		T1	53		T2	1957		T5	56
valid_sources[0x07]	390875	1		T1	80		T2	2114		T5	54
valid_sources[0x08]	391342	1		T1	77		T2	1920		T5	64
valid_sources[0x09]	390796	1		T1	97		T2	1993		T5	66
valid_sources[0x0a]	390021	1		T1	84		T2	1869		T5	76
valid_sources[0x0b]	399638	1		T1	70		T2	2092		T5	48
valid_sources[0x0c]	395053	1		T1	97		T2	1947		T5	72
valid_sources[0x0d]	391992	1		T1	66		T2	2005		T5	49
valid_sources[0x0e]	391506	1		T1	57		T2	1910		T5	56
valid_sources[0x0f]	496690	1		T1	95		T2	1827		T5	51
valid_sources[0x10]	422640	1		T1	58		T2	1907		T5	56
valid_sources[0x11]	392270	1		T1	75		T2	1964		T5	79
valid_sources[0x12]	391519	1		T1	50		T2	1964		T5	70
valid_sources[0x13]	432758	1		T1	107		T2	1855		T3	41455
valid_sources[0x14]	425517	1		T1	55		T2	1952		T5	67
valid_sources[0x15]	396790	1		T1	65		T2	1985		T5	51
valid_sources[0x16]	408472	1		T1	54		T2	1808		T5	62
valid_sources[0x17]	391710	1		T1	68		T2	1744		T5	49
valid_sources[0x18]	618618	1		T1	80		T2	2115		T5	52
valid_sources[0x19]	392717	1		T1	69		T2	1882		T5	45
valid_sources[0x1a]	391915	1		T1	85		T2	1928		T5	60
valid_sources[0x1b]	393615	1		T1	66		T2	1879		T5	50
valid_sources[0x1c]	393488	1		T1	88		T2	1846		T5	52
valid_sources[0x1d]	393952	1		T1	65		T2	1885		T5	56
valid_sources[0x1e]	391383	1		T1	75		T2	1977		T5	61
valid_sources[0x1f]	389932	1		T1	62		T2	1952		T5	59
valid_sources[0x20]	396285	1		T1	55		T2	1881		T5	43
valid_sources[0x21]	392863	1		T1	53		T2	1916		T5	50
valid_sources[0x22]	388411	1		T1	79		T2	1955		T5	50
valid_sources[0x23]	391464	1		T1	60		T2	2002		T5	63
valid_sources[0x24]	391961	1		T1	56		T2	2041		T5	69
valid_sources[0x25]	391899	1		T1	67		T2	1901		T5	50
valid_sources[0x26]	428314	1		T1	88		T2	1866		T5	77
valid_sources[0x27]	390127	1		T1	81		T2	1928		T5	54
valid_sources[0x28]	390447	1		T1	59		T2	1973		T5	62
valid_sources[0x29]	625242	1		T1	65		T2	1851		T5	67
valid_sources[0x2a]	392037	1		T1	97		T2	1963		T5	69
valid_sources[0x2b]	765785	1		T1	70		T2	1974		T5	48
valid_sources[0x2c]	394106	1		T1	52		T2	1952		T5	66
valid_sources[0x2d]	394365	1		T1	68		T2	1927		T5	73
valid_sources[0x2e]	392699	1		T1	75		T2	1861		T5	49
valid_sources[0x2f]	395213	1		T1	50		T2	1981		T5	72
valid_sources[0x30]	498843	1		T1	51		T2	1974		T5	70
valid_sources[0x31]	429698	1		T1	42		T2	1971		T5	68
valid_sources[0x32]	547530	1		T1	83		T2	1972		T5	45
valid_sources[0x33]	392374	1		T1	70		T2	2011		T5	66
valid_sources[0x34]	392116	1		T1	54		T2	2073		T5	62
valid_sources[0x35]	604884	1		T1	63		T2	1921		T5	44
valid_sources[0x36]	414251	1		T1	84		T2	2030		T5	65
valid_sources[0x37]	544157	1		T1	62		T2	1972		T5	56
valid_sources[0x38]	398150	1		T1	76		T2	1957		T5	82
valid_sources[0x39]	2557838	1		T1	52		T2	1898		T5	70
valid_sources[0x3a]	429427	1		T1	53		T2	1965		T5	39
valid_sources[0x3b]	898006	1		T1	45		T2	1875		T5	68
valid_sources[0x3c]	403097	1		T1	74		T2	1830		T5	61
valid_sources[0x3d]	613747	1		T1	76		T2	1891		T5	51
valid_sources[0x3e]	402942	1		T1	102		T2	1931		T5	61
valid_sources[0x3f]	391349	1		T1	70		T2	1835		T5	60
valid_sources[0x40]	395571	1		T1	73		T2	1891		T5	41
valid_sources[0x41]	394868	1		T1	82		T2	2069		T5	50
valid_sources[0x42]	391048	1		T1	89		T2	1906		T5	56
valid_sources[0x43]	1911675	1		T1	72		T2	1940		T5	61
valid_sources[0x44]	389778	1		T1	71		T2	1850		T5	53
valid_sources[0x45]	391000	1		T1	74		T2	1939		T5	58
valid_sources[0x46]	391255	1		T1	74		T2	1842		T5	74
valid_sources[0x47]	389277	1		T1	58		T2	1890		T5	54
valid_sources[0x48]	391763	1		T1	82		T2	1900		T5	58
valid_sources[0x49]	419251	1		T1	50		T2	1925		T5	56
valid_sources[0x4a]	390937	1		T1	46		T2	1940		T5	63
valid_sources[0x4b]	390774	1		T1	66		T2	1865		T5	54
valid_sources[0x4c]	392458	1		T1	58		T2	1907		T5	54
valid_sources[0x4d]	412387	1		T1	98		T2	2105		T5	59
valid_sources[0x4e]	413808	1		T1	60		T2	1973		T5	65
valid_sources[0x4f]	447856	1		T1	63		T2	2056		T5	47
valid_sources[0x50]	391374	1		T1	84		T2	1973		T5	57
valid_sources[0x51]	408067	1		T1	60		T2	1931		T5	66
valid_sources[0x52]	462418	1		T1	92		T2	1819		T5	53
valid_sources[0x53]	391306	1		T1	64		T2	2073		T5	58
valid_sources[0x54]	394716	1		T1	65		T2	1977		T5	54
valid_sources[0x55]	949967	1		T1	69		T2	1997		T4	549118
valid_sources[0x56]	609443	1		T1	51		T2	2083		T5	38
valid_sources[0x57]	450951	1		T1	66		T2	2008		T5	58
valid_sources[0x58]	413359	1		T1	81		T2	1888		T5	53
valid_sources[0x59]	388914	1		T1	76		T2	1913		T5	54
valid_sources[0x5a]	418083	1		T1	71		T2	1920		T5	79
valid_sources[0x5b]	394227	1		T1	65		T2	2062		T5	57
valid_sources[0x5c]	394588	1		T1	69		T2	1870		T5	66
valid_sources[0x5d]	388901	1		T1	75		T2	1871		T5	62
valid_sources[0x5e]	389634	1		T1	59		T2	1867		T5	62
valid_sources[0x5f]	402409	1		T1	69		T2	1926		T5	46
valid_sources[0x60]	392994	1		T1	56		T2	1881		T5	54
valid_sources[0x61]	390810	1		T1	92		T2	1820		T5	62
valid_sources[0x62]	459899	1		T1	68		T2	1933		T5	68
valid_sources[0x63]	392943	1		T1	52		T2	1846		T5	55
valid_sources[0x64]	392387	1		T1	86		T2	1867		T5	56
valid_sources[0x65]	390006	1		T1	64		T2	2009		T5	41
valid_sources[0x66]	394532	1		T1	66		T2	1949		T5	62
valid_sources[0x67]	391612	1		T1	57		T2	1904		T5	60
valid_sources[0x68]	392336	1		T1	65		T2	1893		T5	43
valid_sources[0x69]	389681	1		T1	63		T2	1872		T5	63
valid_sources[0x6a]	391501	1		T1	61		T2	1866		T5	44
valid_sources[0x6b]	392674	1		T1	77		T2	2023		T5	34
valid_sources[0x6c]	476009	1		T1	69		T2	1879		T5	57
valid_sources[0x6d]	392496	1		T1	71		T2	1904		T5	54
valid_sources[0x6e]	392179	1		T1	96		T2	1953		T5	62
valid_sources[0x6f]	392236	1		T1	74		T2	1947		T5	60
valid_sources[0x70]	393300	1		T1	80		T2	1928		T5	53
valid_sources[0x71]	388948	1		T1	71		T2	1914		T5	51
valid_sources[0x72]	459477	1		T1	67		T2	1914		T5	55
valid_sources[0x73]	392581	1		T1	79		T2	1915		T5	54
valid_sources[0x74]	391698	1		T1	48		T2	1863		T5	57
valid_sources[0x75]	393096	1		T1	80		T2	1903		T5	70
valid_sources[0x76]	393463	1		T1	49		T2	1905		T5	52
valid_sources[0x77]	392090	1		T1	73		T2	1927		T5	60
valid_sources[0x78]	392029	1		T1	85		T2	1924		T5	42
valid_sources[0x79]	393112	1		T1	97		T2	1911		T5	52
valid_sources[0x7a]	2201903	1		T1	76		T2	1898		T5	49
valid_sources[0x7b]	461030	1		T1	89		T2	1999		T5	43
valid_sources[0x7c]	391002	1		T1	67		T2	1919		T5	53
valid_sources[0x7d]	392820	1		T1	67		T2	1928		T5	48
valid_sources[0x7e]	492879	1		T1	79		T2	1931		T5	51
valid_sources[0x7f]	392450	1		T1	70		T2	1874		T5	66
valid_sources[0x80]	546349	1		T1	59		T2	1918		T5	52

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64165862

1

T1

9017

T2

247425

T3

20696

values[0x0]

all_enables

biggest_size

615461

1

T1

27

T2

15

T3

13

values[0x1]

all_enables

biggest_size

612007

1

T1

19

T2

19

T3

24