Unified Coverage Report :: Group :: dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg

Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv

19 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
rv_timer-0-prescale-0	100.00	1	100	1	64	64
rv_timer-0-prescale-1	100.00	1	100	1	64	64
rv_timer-0-prescale-10	100.00	1	100	1	64	64
rv_timer-0-prescale-11	100.00	1	100	1	64	64
rv_timer-0-prescale-2	100.00	1	100	1	64	64
rv_timer-0-prescale-3	100.00	1	100	1	64	64
rv_timer-0-prescale-4	100.00	1	100	1	64	64
rv_timer-0-prescale-5	100.00	1	100	1	64	64
rv_timer-0-prescale-6	100.00	1	100	1	64	64
rv_timer-0-prescale-7	100.00	1	100	1	64	64
rv_timer-0-prescale-8	100.00	1	100	1	64	64
rv_timer-0-prescale-9	100.00	1	100	1	64	64
rv_timer_sticky_intr_pin0	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max	100.00	1	100	1	64	64

---

Group Instance : rv_timer-0-prescale-0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-10

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-10

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-10

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-11

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-11

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-11

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-5

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-5

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-6

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-6

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-6

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-7

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-7

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-7

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-8

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-8

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-8

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer-0-prescale-9

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer-0-prescale-9

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer-0-prescale-9

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : rv_timer_sticky_intr_pin0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_timer_sticky_intr_pin0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance rv_timer_sticky_intr_pin0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	0	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	224	1		T2	1		T3	2		T9	2
rising	222	1		T2	1		T3	2		T9	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	644	1		T1	1		T2	1		T3	2
auto[1]	594	1		T2	4		T3	3		T9	2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	224	1		T2	1		T3	1		T9	1
rising	240	1		T2	2		T3	1		T4	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	593	1		T1	1		T2	3		T3	1
auto[1]	645	1		T2	2		T3	4		T4	3

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	247	1		T2	2		T3	1		T4	1
rising	218	1		T2	2		T3	1		T4	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	632	1		T2	2		T3	3		T4	1
auto[1]	606	1		T1	1		T2	3		T3	2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	219	1		T2	1		T3	1		T4	1
rising	213	1		T2	1		T4	1		T7	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	668	1		T2	4		T3	3		T4	2
auto[1]	570	1		T1	1		T2	1		T3	2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	211	1		T2	1		T7	1		T10	1
rising	225	1		T2	1		T9	1		T10	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	621	1		T1	1		T2	3		T3	5
auto[1]	617	1		T2	2		T4	4		T7	1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	215	1		T3	1		T4	1		T10	2
rising	222	1		T2	1		T3	1		T10	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	632	1		T2	3		T3	1		T4	2
auto[1]	606	1		T1	1		T2	2		T3	4

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	239	1		T2	2		T3	2		T4	1
rising	234	1		T2	1		T3	2		T4	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	638	1		T1	1		T2	3		T3	2
auto[1]	600	1		T2	2		T3	3		T4	3

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	209	1		T3	1		T9	2		T10	1
rising	231	1		T3	1		T7	1		T9	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	620	1		T1	1		T3	3		T4	4
auto[1]	618	1		T2	5		T3	2		T6	1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	223	1		T2	1		T3	1		T4	2
rising	240	1		T2	1		T4	1		T9	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	630	1		T2	2		T3	3		T4	2
auto[1]	608	1		T1	1		T2	3		T3	2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	224	1		T2	1		T3	1		T9	1
rising	222	1		T2	1		T3	1		T4	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	585	1		T2	1		T3	4		T4	1
auto[1]	653	1		T1	1		T2	4		T3	1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	220	1		T2	1		T3	1		T4	1
rising	213	1		T2	2		T3	1		T7	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	654	1		T2	2		T3	4		T4	1
auto[1]	584	1		T1	1		T2	3		T3	1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	226	1		T2	1		T9	1		T70	1
rising	216	1		T4	1		T7	1		T9	1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	623	1		T1	1		T2	4		T3	5
auto[1]	615	1		T2	1		T4	2		T7	1

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	61	1		T77	1		T114	1		T115	2
rising	61	1		T77	1		T114	1		T115	2

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	7198	1		T1	19		T2	17		T3	17
auto[1]	95	1		T77	1		T114	2		T115	4

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	399918	1		T12	20467		T13	43955		T14	25118
rising	399914	1		T12	20468		T13	43955		T14	25118

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2721439	1		T12	141259		T13	302061		T14	172923
auto[1]	478685	1		T12	24446		T13	52443		T14	30105

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	766583	1		T12	39485		T13	85117		T14	48574
rising	766581	1		T12	39484		T13	85116		T14	48574

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1902376	1		T12	99168		T13	210049		T14	120550
auto[1]	1297748	1		T12	66537		T13	144455		T14	82478

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	766583	1		T12	39485		T13	85117		T14	48574
rising	766581	1		T12	39484		T13	85116		T14	48574

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1902376	1		T12	99168		T13	210049		T14	120550
auto[1]	1297748	1		T12	66537		T13	144455		T14	82478

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	781053	1		T12	40372		T13	86694		T14	49559
rising	781053	1		T12	40372		T13	86695		T14	49559

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1722472	1		T12	89610		T13	188923		T14	109100
auto[1]	1477652	1		T12	76095		T13	165581		T14	93928

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	565320	1		T12	29227		T13	62676		T14	36079
rising	565324	1		T12	29227		T13	62677		T14	36079

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2460083	1		T12	127363		T13	272325		T14	155615
auto[1]	740041	1		T12	38342		T13	82179		T14	47413

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
falling	577064	1		T12	29955		T13	64442		T14	36522
rising	577056	1		T12	29955		T13	64441		T14	36521

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2444217	1		T12	126624		T13	270343		T14	155009
auto[1]	755907	1		T12	39081		T13	84161		T14	48019