Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2120026	0	0
cfg0_rd_A	2147483647	8372	0	0
compare_lower0_0_rd_A	2147483647	8967	0	0
compare_upper0_0_rd_A	2147483647	8804	0	0
ctrl_rd_A	2147483647	8297	0	0
intr_enable0_rd_A	2147483647	9940	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2120026	0	0
T12	570817	108746	0	0
T13	0	233018	0	0
T14	0	133298	0	0
T35	0	127499	0	0
T36	0	196952	0	0
T37	0	253022	0	0
T38	0	58412	0	0
T39	0	51468	0	0
T40	0	115009	0	0
T41	0	102956	0	0
T42	832693	0	0	0
T43	827845	0	0	0
T44	973429	0	0	0
T45	437754	0	0	0
T46	114863	0	0	0
T47	786995	0	0	0
T48	477167	0	0	0
T49	818775	0	0	0
T50	108137	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8372	0	0
T30	0	31	0	0
T33	0	21	0	0
T36	773243	1918	0	0
T37	890928	0	0	0
T38	0	689	0	0
T40	0	1108	0	0
T51	0	311	0	0
T52	0	2688	0	0
T53	0	5	0	0
T54	0	22	0	0
T55	0	28	0	0
T56	408290	0	0	0
T57	335878	0	0	0
T58	149793	0	0	0
T59	241111	0	0	0
T60	645424	0	0	0
T61	391718	0	0	0
T62	614933	0	0	0
T63	107228	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8967	0	0
T30	0	6	0	0
T33	0	19	0	0
T36	773243	2024	0	0
T37	890928	0	0	0
T38	0	673	0	0
T40	0	1306	0	0
T51	0	370	0	0
T52	0	3119	0	0
T53	0	4	0	0
T54	0	29	0	0
T55	0	13	0	0
T56	408290	0	0	0
T57	335878	0	0	0
T58	149793	0	0	0
T59	241111	0	0	0
T60	645424	0	0	0
T61	391718	0	0	0
T62	614933	0	0	0
T63	107228	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8804	0	0
T30	0	35	0	0
T33	0	23	0	0
T36	773243	2098	0	0
T37	890928	0	0	0
T38	0	620	0	0
T40	0	1247	0	0
T51	0	368	0	0
T52	0	2963	0	0
T54	0	46	0	0
T55	0	16	0	0
T56	408290	0	0	0
T57	335878	0	0	0
T58	149793	0	0	0
T59	241111	0	0	0
T60	645424	0	0	0
T61	391718	0	0	0
T62	614933	0	0	0
T63	107228	0	0	0
T64	0	55	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8297	0	0
T30	0	12	0	0
T33	0	29	0	0
T36	773243	2075	0	0
T37	890928	0	0	0
T38	0	615	0	0
T40	0	1168	0	0
T51	0	306	0	0
T52	0	2644	0	0
T53	0	1	0	0
T54	0	22	0	0
T55	0	10	0	0
T56	408290	0	0	0
T57	335878	0	0	0
T58	149793	0	0	0
T59	241111	0	0	0
T60	645424	0	0	0
T61	391718	0	0	0
T62	614933	0	0	0
T63	107228	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9940	0	0
T11	912735	21	0	0
T34	1960	12	0	0
T36	0	2274	0	0
T38	0	760	0	0
T40	0	1361	0	0
T65	0	11	0	0
T66	0	76	0	0
T67	0	47	0	0
T68	0	65	0	0
T69	0	10	0	0
T70	101687	0	0	0
T71	171023	0	0	0
T72	102870	0	0	0
T73	507606	0	0	0
T74	405320	0	0	0
T75	787579	0	0	0
T76	846256	0	0	0
T77	106477	0	0	0