Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	71126945	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	72894316	1		T1	330918		T2	12775		T3	17327

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	142493122	1		T1	662494		T2	25507		T3	34471
values[0x0]	726391	1		T1	81		T2	15		T3	23
values[0x1]	801748	1		T1	67		T2	14		T3	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56792286	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	87228975	1		T1	397290		T2	15245		T3	20735

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	446052	1		T1	2521		T2	110		T4	216
valid_sources[0x01]	366893	1		T1	2683		T2	76		T4	259
valid_sources[0x02]	1094854	1		T1	2548		T2	99		T4	195
valid_sources[0x03]	369748	1		T1	2651		T2	70		T4	205
valid_sources[0x04]	370669	1		T1	2681		T2	94		T4	222
valid_sources[0x05]	437258	1		T1	2677		T2	126		T4	252
valid_sources[0x06]	365049	1		T1	2560		T2	86		T4	203
valid_sources[0x07]	367706	1		T1	2646		T2	107		T4	233
valid_sources[0x08]	369643	1		T1	2503		T2	106		T4	198
valid_sources[0x09]	366163	1		T1	2548		T2	97		T4	192
valid_sources[0x0a]	368287	1		T1	2526		T2	105		T4	228
valid_sources[0x0b]	720746	1		T1	2636		T2	105		T4	179
valid_sources[0x0c]	365699	1		T1	2544		T2	119		T4	169
valid_sources[0x0d]	370533	1		T1	2583		T2	120		T4	196
valid_sources[0x0e]	2104359	1		T1	2681		T2	95		T4	201
valid_sources[0x0f]	663744	1		T1	2677		T2	58		T4	237
valid_sources[0x10]	1048897	1		T1	2486		T2	93		T4	189
valid_sources[0x11]	367563	1		T1	2397		T2	87		T4	236
valid_sources[0x12]	370224	1		T1	2579		T2	123		T4	160
valid_sources[0x13]	367477	1		T1	2618		T2	117		T4	204
valid_sources[0x14]	369766	1		T1	2512		T2	97		T4	211
valid_sources[0x15]	369494	1		T1	2645		T2	109		T4	195
valid_sources[0x16]	929048	1		T1	2607		T2	121		T4	220
valid_sources[0x17]	417809	1		T1	2540		T2	120		T4	163
valid_sources[0x18]	368411	1		T1	2587		T2	93		T4	207
valid_sources[0x19]	367767	1		T1	2545		T2	88		T4	227
valid_sources[0x1a]	368511	1		T1	2552		T2	108		T4	150
valid_sources[0x1b]	368219	1		T1	2520		T2	127		T4	176
valid_sources[0x1c]	368290	1		T1	2472		T2	103		T4	204
valid_sources[0x1d]	366461	1		T1	2518		T2	96		T4	191
valid_sources[0x1e]	1887444	1		T1	2703		T2	104		T4	214
valid_sources[0x1f]	367778	1		T1	2819		T2	98		T4	212
valid_sources[0x20]	367705	1		T1	2592		T2	114		T4	179
valid_sources[0x21]	868725	1		T1	2546		T2	89		T4	216
valid_sources[0x22]	387786	1		T1	2423		T2	108		T4	208
valid_sources[0x23]	368393	1		T1	2574		T2	79		T4	231
valid_sources[0x24]	366263	1		T1	2574		T2	99		T4	200
valid_sources[0x25]	365801	1		T1	2604		T2	107		T4	206
valid_sources[0x26]	367500	1		T1	2552		T2	116		T4	200
valid_sources[0x27]	602560	1		T1	2680		T2	109		T4	216
valid_sources[0x28]	369425	1		T1	2505		T2	94		T4	201
valid_sources[0x29]	372242	1		T1	2747		T2	96		T4	176
valid_sources[0x2a]	1641513	1		T1	2562		T2	88		T4	203
valid_sources[0x2b]	365239	1		T1	2554		T2	92		T4	223
valid_sources[0x2c]	364467	1		T1	2599		T2	75		T4	258
valid_sources[0x2d]	1835188	1		T1	2624		T2	79		T4	188
valid_sources[0x2e]	369051	1		T1	2700		T2	84		T4	202
valid_sources[0x2f]	529243	1		T1	2657		T2	103		T4	202
valid_sources[0x30]	366276	1		T1	2566		T2	92		T4	210
valid_sources[0x31]	369242	1		T1	2605		T2	95		T4	240
valid_sources[0x32]	370649	1		T1	2562		T2	71		T4	185
valid_sources[0x33]	377990	1		T1	2548		T2	88		T4	235
valid_sources[0x34]	370992	1		T1	2494		T2	77		T4	239
valid_sources[0x35]	443212	1		T1	2723		T2	146		T4	190
valid_sources[0x36]	365311	1		T1	2551		T2	111		T4	222
valid_sources[0x37]	2274530	1		T1	2699		T2	104		T4	204
valid_sources[0x38]	367482	1		T1	2449		T2	89		T4	243
valid_sources[0x39]	370135	1		T1	2729		T2	94		T4	235
valid_sources[0x3a]	2075852	1		T1	2522		T2	110		T4	222
valid_sources[0x3b]	1465458	1		T1	2557		T2	143		T4	208
valid_sources[0x3c]	365559	1		T1	2378		T2	99		T4	246
valid_sources[0x3d]	2177848	1		T1	2509		T2	100		T4	212
valid_sources[0x3e]	366552	1		T1	2626		T2	72		T4	208
valid_sources[0x3f]	366355	1		T1	2732		T2	114		T4	226
valid_sources[0x40]	365642	1		T1	2500		T2	99		T4	204
valid_sources[0x41]	826147	1		T1	2540		T2	83		T4	220
valid_sources[0x42]	370321	1		T1	2670		T2	95		T4	236
valid_sources[0x43]	370229	1		T1	2618		T2	80		T4	213
valid_sources[0x44]	370133	1		T1	2529		T2	86		T4	209
valid_sources[0x45]	369401	1		T1	2761		T2	120		T4	221
valid_sources[0x46]	376864	1		T1	2558		T2	102		T4	224
valid_sources[0x47]	367571	1		T1	2771		T2	150		T4	221
valid_sources[0x48]	367344	1		T1	2662		T2	77		T4	220
valid_sources[0x49]	368116	1		T1	2551		T2	82		T4	215
valid_sources[0x4a]	369778	1		T1	2676		T2	114		T4	223
valid_sources[0x4b]	409584	1		T1	2683		T2	107		T4	200
valid_sources[0x4c]	386331	1		T1	2641		T2	121		T4	171
valid_sources[0x4d]	367959	1		T1	2588		T2	90		T4	225
valid_sources[0x4e]	370042	1		T1	2563		T2	122		T4	213
valid_sources[0x4f]	370506	1		T1	2527		T2	103		T4	208
valid_sources[0x50]	388482	1		T1	2552		T2	78		T4	210
valid_sources[0x51]	366416	1		T1	2652		T2	93		T4	203
valid_sources[0x52]	364627	1		T1	2762		T2	99		T4	227
valid_sources[0x53]	368253	1		T1	2464		T2	95		T4	207
valid_sources[0x54]	438701	1		T1	2525		T2	112		T4	222
valid_sources[0x55]	368901	1		T1	2636		T2	91		T4	231
valid_sources[0x56]	368263	1		T1	2616		T2	92		T4	219
valid_sources[0x57]	368978	1		T1	2572		T2	83		T4	188
valid_sources[0x58]	365956	1		T1	2579		T2	129		T4	184
valid_sources[0x59]	437158	1		T1	2675		T2	94		T4	209
valid_sources[0x5a]	366511	1		T1	2570		T2	85		T4	189
valid_sources[0x5b]	368691	1		T1	2496		T2	109		T4	209
valid_sources[0x5c]	636214	1		T1	2507		T2	105		T4	199
valid_sources[0x5d]	1156481	1		T1	2609		T2	88		T4	230
valid_sources[0x5e]	368442	1		T1	2576		T2	95		T4	248
valid_sources[0x5f]	695092	1		T1	2699		T2	114		T4	222
valid_sources[0x60]	401316	1		T1	2566		T2	97		T4	208
valid_sources[0x61]	370410	1		T1	2632		T2	115		T4	193
valid_sources[0x62]	367615	1		T1	2551		T2	114		T4	205
valid_sources[0x63]	367715	1		T1	2566		T2	95		T4	248
valid_sources[0x64]	364604	1		T1	2698		T2	75		T4	174
valid_sources[0x65]	369409	1		T1	2660		T2	79		T4	198
valid_sources[0x66]	366861	1		T1	2602		T2	80		T4	202
valid_sources[0x67]	663304	1		T1	2581		T2	80		T4	201
valid_sources[0x68]	368081	1		T1	2571		T2	94		T4	214
valid_sources[0x69]	372135	1		T1	2712		T2	102		T4	204
valid_sources[0x6a]	387858	1		T1	2517		T2	90		T4	268
valid_sources[0x6b]	374540	1		T1	2695		T2	142		T4	247
valid_sources[0x6c]	400109	1		T1	2651		T2	96		T3	34521
valid_sources[0x6d]	369757	1		T1	2562		T2	109		T4	222
valid_sources[0x6e]	367286	1		T1	2584		T2	102		T4	208
valid_sources[0x6f]	364196	1		T1	2442		T2	121		T4	228
valid_sources[0x70]	369235	1		T1	2562		T2	104		T4	187
valid_sources[0x71]	653510	1		T1	2567		T2	95		T4	200
valid_sources[0x72]	366197	1		T1	2659		T2	103		T4	212
valid_sources[0x73]	841107	1		T1	2653		T2	97		T4	213
valid_sources[0x74]	365637	1		T1	2554		T2	129		T4	194
valid_sources[0x75]	369623	1		T1	2494		T2	76		T4	224
valid_sources[0x76]	379613	1		T1	2540		T2	81		T4	221
valid_sources[0x77]	4893969	1		T1	2567		T2	89		T4	230
valid_sources[0x78]	389233	1		T1	2693		T2	102		T4	209
valid_sources[0x79]	366015	1		T1	2496		T2	117		T4	196
valid_sources[0x7a]	425579	1		T1	2654		T2	69		T4	256
valid_sources[0x7b]	370168	1		T1	2526		T2	142		T4	198
valid_sources[0x7c]	363912	1		T1	2551		T2	106		T4	165
valid_sources[0x7d]	2414937	1		T1	2758		T2	115		T4	203
valid_sources[0x7e]	369590	1		T1	2637		T2	83		T4	199
valid_sources[0x7f]	369489	1		T1	2554		T2	92		T4	219
valid_sources[0x80]	370775	1		T1	2454		T2	99		T4	229

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71470372

1

T1

330818

T2

12749

T3

17289

values[0x0]

all_enables

biggest_size

713174

1

T1

62

T2

12

T3

18

values[0x1]

all_enables

biggest_size

710770

1

T1

38

T2

14

T3

20