Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2496354	0	0
cfg0_rd_A	2147483647	6884	0	0
compare_lower0_0_rd_A	2147483647	7063	0	0
compare_upper0_0_rd_A	2147483647	5943	0	0
ctrl_rd_A	2147483647	6591	0	0
intr_enable0_rd_A	2147483647	8218	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2496354	0	0
T13	271430	69495	0	0
T14	0	664215	0	0
T15	0	393641	0	0
T16	7011	0	0	0
T21	303425	0	0	0
T22	157213	0	0	0
T23	101698	0	0	0
T24	103033	0	0	0
T25	104022	0	0	0
T26	342219	0	0	0
T27	441963	0	0	0
T35	0	61871	0	0
T36	0	131377	0	0
T37	0	40253	0	0
T38	0	75901	0	0
T39	0	190160	0	0
T40	0	21799	0	0
T41	0	53824	0	0
T42	242059	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6884	0	0
T13	271430	751	0	0
T16	7011	0	0	0
T21	303425	0	0	0
T22	157213	0	0	0
T23	101698	0	0	0
T24	103033	0	0	0
T25	104022	0	0	0
T26	342219	0	0	0
T27	441963	0	0	0
T31	0	52	0	0
T35	0	558	0	0
T37	0	229	0	0
T38	0	455	0	0
T39	0	1922	0	0
T40	0	259	0	0
T42	242059	0	0	0
T43	0	4	0	0
T44	0	8	0	0
T45	0	7	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7063	0	0
T13	271430	890	0	0
T16	7011	0	0	0
T21	303425	0	0	0
T22	157213	0	0	0
T23	101698	0	0	0
T24	103033	0	0	0
T25	104022	0	0	0
T26	342219	0	0	0
T27	441963	0	0	0
T31	0	31	0	0
T35	0	710	0	0
T37	0	204	0	0
T38	0	563	0	0
T39	0	2107	0	0
T40	0	302	0	0
T42	242059	0	0	0
T43	0	6	0	0
T44	0	18	0	0
T46	0	7	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5943	0	0
T13	271430	751	0	0
T16	7011	0	0	0
T21	303425	0	0	0
T22	157213	0	0	0
T23	101698	0	0	0
T24	103033	0	0	0
T25	104022	0	0	0
T26	342219	0	0	0
T27	441963	0	0	0
T31	0	31	0	0
T35	0	585	0	0
T37	0	250	0	0
T38	0	320	0	0
T39	0	1654	0	0
T40	0	320	0	0
T42	242059	0	0	0
T43	0	7	0	0
T45	0	7	0	0
T46	0	11	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6591	0	0
T13	271430	751	0	0
T16	7011	0	0	0
T21	303425	0	0	0
T22	157213	0	0	0
T23	101698	0	0	0
T24	103033	0	0	0
T25	104022	0	0	0
T26	342219	0	0	0
T27	441963	0	0	0
T31	0	32	0	0
T35	0	693	0	0
T37	0	204	0	0
T38	0	486	0	0
T39	0	1986	0	0
T40	0	209	0	0
T42	242059	0	0	0
T43	0	12	0	0
T44	0	1	0	0
T45	0	9	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8218	0	0
T11	488582	110	0	0
T12	102595	0	0	0
T13	271430	816	0	0
T16	7011	0	0	0
T21	303425	0	0	0
T35	0	858	0	0
T37	0	293	0	0
T38	0	508	0	0
T39	0	2490	0	0
T40	0	362	0	0
T42	242059	0	0	0
T47	611320	37	0	0
T48	0	50	0	0
T49	0	18	0	0
T50	176132	0	0	0
T51	332923	0	0	0
T52	220283	0	0	0