Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 63907249 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 65215723 1 T1 2199 T2 229099 T3 16614



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 127986707 1 T1 4342 T2 457419 T3 33076
values[0x0] 540524 1 T1 13 T2 23 T3 10
values[0x1] 595741 1 T1 6 T2 19 T3 15



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 51042373 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 78080599 1 T1 2640 T2 275054 T3 19874



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 338618 1 T1 17 T2 1807 T3 120
valid_sources[0x01] 341687 1 T1 11 T2 1758 T3 135
valid_sources[0x02] 597862 1 T1 18 T2 1776 T3 139
valid_sources[0x03] 341653 1 T1 15 T2 1741 T3 139
valid_sources[0x04] 366310 1 T1 19 T2 1870 T3 136
valid_sources[0x05] 340953 1 T1 21 T2 1837 T3 117
valid_sources[0x06] 340880 1 T1 15 T2 1771 T3 135
valid_sources[0x07] 344631 1 T1 17 T2 1885 T3 120
valid_sources[0x08] 339948 1 T1 17 T2 1714 T3 120
valid_sources[0x09] 338517 1 T1 15 T2 1734 T3 131
valid_sources[0x0a] 9758249 1 T1 12 T2 1754 T3 112
valid_sources[0x0b] 339193 1 T1 18 T2 1812 T3 124
valid_sources[0x0c] 343007 1 T1 20 T2 1763 T3 156
valid_sources[0x0d] 341437 1 T1 12 T2 1867 T3 120
valid_sources[0x0e] 344210 1 T1 23 T2 1699 T3 148
valid_sources[0x0f] 393014 1 T1 11 T2 1800 T3 119
valid_sources[0x10] 339201 1 T1 15 T2 1815 T3 156
valid_sources[0x11] 538040 1 T1 18 T2 1776 T3 129
valid_sources[0x12] 340587 1 T1 21 T2 1815 T3 134
valid_sources[0x13] 1620520 1 T1 26 T2 1757 T3 129
valid_sources[0x14] 341193 1 T1 26 T2 1785 T3 132
valid_sources[0x15] 342796 1 T1 11 T2 1812 T3 119
valid_sources[0x16] 340568 1 T1 17 T2 1798 T3 120
valid_sources[0x17] 341261 1 T1 18 T2 1769 T3 145
valid_sources[0x18] 339981 1 T1 17 T2 1788 T3 127
valid_sources[0x19] 343295 1 T1 21 T2 1726 T3 144
valid_sources[0x1a] 340585 1 T1 9 T2 1837 T3 131
valid_sources[0x1b] 342962 1 T1 10 T2 1849 T3 121
valid_sources[0x1c] 340749 1 T1 18 T2 1814 T3 96
valid_sources[0x1d] 338509 1 T1 15 T2 1819 T3 121
valid_sources[0x1e] 340072 1 T1 13 T2 1821 T3 128
valid_sources[0x1f] 340829 1 T1 18 T2 1825 T3 99
valid_sources[0x20] 338889 1 T1 18 T2 1746 T3 125
valid_sources[0x21] 342063 1 T1 17 T2 1864 T3 137
valid_sources[0x22] 341687 1 T1 21 T2 1749 T3 144
valid_sources[0x23] 519740 1 T1 13 T2 1821 T3 172
valid_sources[0x24] 338842 1 T1 10 T2 1834 T3 109
valid_sources[0x25] 343095 1 T1 10 T2 1863 T3 131
valid_sources[0x26] 341781 1 T1 14 T2 1744 T3 142
valid_sources[0x27] 337899 1 T1 23 T2 1697 T3 124
valid_sources[0x28] 339543 1 T1 13 T2 1790 T3 144
valid_sources[0x29] 340570 1 T1 11 T2 1785 T3 128
valid_sources[0x2a] 337353 1 T1 10 T2 1793 T3 100
valid_sources[0x2b] 341721 1 T1 24 T2 1847 T3 149
valid_sources[0x2c] 340273 1 T1 21 T2 1799 T3 119
valid_sources[0x2d] 502360 1 T1 16 T2 1741 T3 122
valid_sources[0x2e] 359628 1 T1 16 T2 1764 T3 135
valid_sources[0x2f] 340513 1 T1 15 T2 1727 T3 103
valid_sources[0x30] 587872 1 T1 18 T2 1815 T3 132
valid_sources[0x31] 1612157 1 T1 11 T2 1854 T3 148
valid_sources[0x32] 714611 1 T1 22 T2 1837 T3 127
valid_sources[0x33] 344216 1 T1 18 T2 1803 T3 120
valid_sources[0x34] 340517 1 T1 14 T2 1789 T3 147
valid_sources[0x35] 342502 1 T1 20 T2 1772 T3 136
valid_sources[0x36] 339171 1 T1 12 T2 1702 T3 132
valid_sources[0x37] 418954 1 T1 16 T2 1746 T3 129
valid_sources[0x38] 339915 1 T1 15 T2 1801 T3 125
valid_sources[0x39] 340916 1 T1 13 T2 1853 T3 118
valid_sources[0x3a] 341547 1 T1 15 T2 1828 T3 113
valid_sources[0x3b] 343407 1 T1 19 T2 1744 T3 111
valid_sources[0x3c] 338699 1 T1 18 T2 1783 T3 127
valid_sources[0x3d] 339232 1 T1 23 T2 1791 T3 147
valid_sources[0x3e] 341004 1 T1 18 T2 1803 T3 122
valid_sources[0x3f] 339016 1 T1 24 T2 1808 T3 147
valid_sources[0x40] 2589205 1 T1 13 T2 1644 T3 127
valid_sources[0x41] 341625 1 T1 12 T2 1862 T3 122
valid_sources[0x42] 338165 1 T1 19 T2 1743 T3 138
valid_sources[0x43] 339855 1 T1 21 T2 1743 T3 123
valid_sources[0x44] 460086 1 T1 15 T2 1853 T3 143
valid_sources[0x45] 465185 1 T1 24 T2 1706 T3 143
valid_sources[0x46] 338532 1 T1 29 T2 1801 T3 131
valid_sources[0x47] 339486 1 T1 17 T2 1844 T3 130
valid_sources[0x48] 696781 1 T1 16 T2 1794 T3 138
valid_sources[0x49] 406365 1 T1 19 T2 1721 T3 116
valid_sources[0x4a] 342363 1 T1 19 T2 1889 T3 122
valid_sources[0x4b] 340835 1 T1 13 T2 1764 T3 127
valid_sources[0x4c] 342928 1 T1 14 T2 1810 T3 157
valid_sources[0x4d] 347161 1 T1 23 T2 1834 T3 135
valid_sources[0x4e] 337762 1 T1 14 T2 1824 T3 124
valid_sources[0x4f] 484594 1 T1 23 T2 1806 T3 157
valid_sources[0x50] 340340 1 T1 7 T2 1764 T3 97
valid_sources[0x51] 414519 1 T1 19 T2 1758 T3 114
valid_sources[0x52] 340767 1 T1 22 T2 1833 T3 155
valid_sources[0x53] 339144 1 T1 12 T2 1741 T3 135
valid_sources[0x54] 341885 1 T1 29 T2 1724 T3 154
valid_sources[0x55] 344684 1 T1 18 T2 1862 T3 135
valid_sources[0x56] 340943 1 T1 23 T2 1777 T3 131
valid_sources[0x57] 1520939 1 T1 22 T2 1873 T3 138
valid_sources[0x58] 341881 1 T1 9 T2 1829 T3 157
valid_sources[0x59] 342473 1 T1 16 T2 1699 T3 119
valid_sources[0x5a] 414112 1 T1 17 T2 1835 T3 137
valid_sources[0x5b] 395373 1 T1 27 T2 1858 T3 122
valid_sources[0x5c] 4331549 1 T1 23 T2 1732 T3 139
valid_sources[0x5d] 339243 1 T1 18 T2 1884 T3 126
valid_sources[0x5e] 2299458 1 T1 15 T2 1674 T3 131
valid_sources[0x5f] 340236 1 T1 18 T2 1781 T3 141
valid_sources[0x60] 340616 1 T1 22 T2 1764 T3 110
valid_sources[0x61] 338194 1 T1 19 T2 1812 T3 145
valid_sources[0x62] 438721 1 T1 13 T2 1801 T3 146
valid_sources[0x63] 340403 1 T1 13 T2 1791 T3 122
valid_sources[0x64] 343543 1 T1 12 T2 1762 T3 114
valid_sources[0x65] 449665 1 T1 21 T2 1855 T3 110
valid_sources[0x66] 341430 1 T1 17 T2 1853 T3 130
valid_sources[0x67] 341700 1 T1 17 T2 1749 T3 117
valid_sources[0x68] 343781 1 T1 20 T2 1714 T3 137
valid_sources[0x69] 1455707 1 T1 19 T2 1761 T3 107
valid_sources[0x6a] 340267 1 T1 20 T2 1748 T3 140
valid_sources[0x6b] 341047 1 T1 25 T2 1814 T3 128
valid_sources[0x6c] 342679 1 T1 12 T2 1829 T3 119
valid_sources[0x6d] 458581 1 T1 20 T2 1815 T3 111
valid_sources[0x6e] 370793 1 T1 19 T2 1826 T3 119
valid_sources[0x6f] 443942 1 T1 17 T2 1800 T3 118
valid_sources[0x70] 1823469 1 T1 20 T2 1738 T3 126
valid_sources[0x71] 337346 1 T1 13 T2 1739 T3 117
valid_sources[0x72] 541378 1 T1 26 T2 1731 T3 147
valid_sources[0x73] 395755 1 T1 20 T2 1721 T3 109
valid_sources[0x74] 341605 1 T1 30 T2 1798 T3 127
valid_sources[0x75] 340460 1 T1 18 T2 1750 T3 122
valid_sources[0x76] 340348 1 T1 21 T2 1768 T3 133
valid_sources[0x77] 356214 1 T1 18 T2 1756 T3 142
valid_sources[0x78] 567297 1 T1 13 T2 1778 T3 138
valid_sources[0x79] 342775 1 T1 13 T2 1722 T3 122
valid_sources[0x7a] 343557 1 T1 19 T2 1828 T3 152
valid_sources[0x7b] 339001 1 T1 20 T2 1729 T3 146
valid_sources[0x7c] 416477 1 T1 18 T2 1753 T3 114
valid_sources[0x7d] 342449 1 T1 21 T2 1813 T3 128
valid_sources[0x7e] 359437 1 T1 28 T2 1813 T3 127
valid_sources[0x7f] 383172 1 T1 22 T2 1704 T3 106
valid_sources[0x80] 339300 1 T1 17 T2 1727 T3 113



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 64158940 1 T1 2184 T2 229072 T3 16590
values[0x0] all_enables biggest_size 529566 1 T1 10 T2 14 T3 10
values[0x1] all_enables biggest_size 527217 1 T1 5 T2 13 T3 14

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%