Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1841571	0	0
cfg0_rd_A	2147483647	2920	0	0
compare_lower0_0_rd_A	2147483647	2554	0	0
compare_upper0_0_rd_A	2147483647	2571	0	0
ctrl_rd_A	2147483647	2536	0	0
intr_enable0_rd_A	2147483647	3699	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1841571	0	0
T12	791357	315001	0	0
T13	375211	16217	0	0
T14	0	123277	0	0
T15	5633	0	0	0
T20	589750	0	0	0
T21	15708	0	0	0
T22	135876	0	0	0
T23	7483	0	0	0
T33	0	211136	0	0
T34	0	142010	0	0
T35	0	61605	0	0
T36	0	42092	0	0
T37	0	232736	0	0
T38	0	107888	0	0
T39	0	64889	0	0
T40	117321	0	0	0
T41	406560	0	0	0
T42	319213	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2920	0	0
T29	0	149	0	0
T30	0	155	0	0
T32	0	4	0	0
T39	242605	707	0	0
T43	0	9	0	0
T44	0	23	0	0
T45	0	118	0	0
T46	0	23	0	0
T47	0	5	0	0
T48	0	107	0	0
T49	811566	0	0	0
T50	2162	0	0	0
T51	109812	0	0	0
T52	403588	0	0	0
T53	955936	0	0	0
T54	171050	0	0	0
T55	139900	0	0	0
T56	210071	0	0	0
T57	404695	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2554	0	0
T29	0	65	0	0
T30	0	131	0	0
T32	0	5	0	0
T39	242605	733	0	0
T43	0	5	0	0
T44	0	10	0	0
T45	0	102	0	0
T46	0	17	0	0
T48	0	83	0	0
T49	811566	0	0	0
T50	2162	0	0	0
T51	109812	0	0	0
T52	403588	0	0	0
T53	955936	0	0	0
T54	171050	0	0	0
T55	139900	0	0	0
T56	210071	0	0	0
T57	404695	0	0	0
T58	0	3	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2571	0	0
T29	0	91	0	0
T30	0	106	0	0
T32	0	11	0	0
T39	242605	485	0	0
T43	0	8	0	0
T44	0	5	0	0
T45	0	130	0	0
T46	0	21	0	0
T47	0	14	0	0
T48	0	93	0	0
T49	811566	0	0	0
T50	2162	0	0	0
T51	109812	0	0	0
T52	403588	0	0	0
T53	955936	0	0	0
T54	171050	0	0	0
T55	139900	0	0	0
T56	210071	0	0	0
T57	404695	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2536	0	0
T29	0	90	0	0
T30	0	137	0	0
T32	0	7	0	0
T39	242605	660	0	0
T43	0	9	0	0
T44	0	6	0	0
T45	0	127	0	0
T46	0	9	0	0
T48	0	67	0	0
T49	811566	0	0	0
T50	2162	0	0	0
T51	109812	0	0	0
T52	403588	0	0	0
T53	955936	0	0	0
T54	171050	0	0	0
T55	139900	0	0	0
T56	210071	0	0	0
T57	404695	0	0	0
T59	0	74	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3699	0	0
T60	698150	57	0	0
T61	0	71	0	0
T62	0	3	0	0
T63	0	81	0	0
T64	0	21	0	0
T65	0	77	0	0
T66	0	20	0	0
T67	0	93	0	0
T68	0	85	0	0
T69	0	22	0	0
T70	378458	0	0	0
T71	111542	0	0	0
T72	9585	0	0	0
T73	565455	0	0	0
T74	404822	0	0	0
T75	995343	0	0	0
T76	441293	0	0	0
T77	109938	0	0	0
T78	126661	0	0	0