Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
80.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_errors_cgs_wrap[rv_timer_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_errors_cgs_wrap[rv_timer_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_errors_cgs_wrap[rv_timer_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 3 12 100.00


Variables for Group Instance tl_errors_cgs_wrap[rv_timer_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_csr_size_err 2 0 2 100.00 100 1 1 2
cp_instr_type_err 2 0 2 100.00 100 1 1 2
cp_mem_byte_access_err 2 1 1 50.00 100 0 0 2
cp_mem_ro_err 2 1 1 50.00 100 0 0 2
cp_mem_wo_err 2 1 1 50.00 100 0 0 2
cp_tl_protocol_err 1 0 1 100.00 100 1 1 0
cp_unmapped_err 2 0 2 100.00 100 1 1 2
cp_write_w_instr_type_err 2 0 2 100.00 100 1 1 2


Summary for Variable cp_csr_size_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_csr_size_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 180176 1 T4 3669 T12 4591 T13 10605
auto[1] 35723 1 T4 689 T12 856 T13 2167



Summary for Variable cp_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_instr_type_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 172238 1 T4 3462 T12 4269 T13 10151
auto[1] 43661 1 T4 896 T12 1178 T13 2621



Summary for Variable cp_mem_byte_access_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_byte_access_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 215899 0 T4 4358 T12 5447 T13 12772



Summary for Variable cp_mem_ro_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_ro_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 215899 0 T4 4358 T12 5447 T13 12772



Summary for Variable cp_mem_wo_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_wo_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 215899 0 T4 4358 T12 5447 T13 12772



Summary for Variable cp_tl_protocol_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_tl_protocol_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
covered 54516 1 T4 1174 T12 1330 T13 3106



Summary for Variable cp_unmapped_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_unmapped_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 177648 1 T4 3641 T12 4486 T13 10546
auto[1] 38251 1 T4 717 T12 961 T13 2226



Summary for Variable cp_write_w_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write_w_instr_type_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 172164 1 T4 3476 T12 4325 T13 10120
auto[1] 43735 1 T4 882 T12 1122 T13 2652

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