SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_timer_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 135289828 | 0 | T1 | 668495 | T2 | 8951 | T3 | 68366 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 135289535 | 1 | T1 | 668495 | T2 | 8951 | T3 | 68366 | |||
values[1] | 30 | 1 | T28 | 2 | T29 | 3 | T30 | 2 | |||
values[2] | 2 | 1 | T88 | 1 | T89 | 1 | - | - | |||
values[3] | 143 | 1 | T28 | 3 | T29 | 8 | T30 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 135289530 | 1 | T1 | 668495 | T2 | 8951 | T3 | 68366 | |||
values[1] | 32 | 1 | T28 | 2 | T29 | 1 | T90 | 2 | |||
values[2] | 9 | 1 | T28 | 1 | T29 | 1 | T90 | 1 | |||
values[3] | 160 | 1 | T28 | 6 | T29 | 10 | T30 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 135289388 | 1 | T1 | 668495 | T2 | 8951 | T3 | 68366 | |||
auto[TlIntgErrCmd] | 142 | 1 | T28 | 6 | T29 | 6 | T30 | 7 | |||
auto[TlIntgErrData] | 147 | 1 | T28 | 7 | T29 | 5 | T30 | 6 | |||
auto[TlIntgErrBoth] | 151 | 1 | T28 | 7 | T29 | 9 | T30 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |