Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_timer_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.71 99.24 99.29 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.83 100.00 83.33 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test 100.00 100.00
u_cfg0_prescale 100.00 100.00 100.00 100.00
u_cfg0_step 100.00 100.00 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_compare_lower0_0 100.00 100.00 100.00 100.00
u_compare_lower0_00_qe 100.00 100.00 100.00
u_compare_upper0_0 100.00 100.00 100.00 100.00
u_compare_upper0_00_qe 100.00 100.00 100.00
u_ctrl 100.00 100.00 100.00 100.00
u_intr_enable0 100.00 100.00 100.00 100.00
u_intr_state0 100.00 100.00 100.00 100.00
u_intr_test0 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.67 97.14 97.53 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_timer_v_lower0 100.00 100.00 100.00 100.00
u_timer_v_upper0 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_timer_reg_top
Line No.TotalCoveredPercent
TOTAL7575100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN47311100.00
ALWAYS4791111100.00
CONT_ASSIGN49211100.00
ALWAYS49611100.00
CONT_ASSIGN51011100.00
CONT_ASSIGN51211100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51611100.00
CONT_ASSIGN51811100.00
CONT_ASSIGN51911100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN52211100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN53011100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53311100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN53611100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53911100.00
CONT_ASSIGN54111100.00
ALWAYS5451111100.00
ALWAYS5601313100.00
CONT_ASSIGN61400
CONT_ASSIGN62211100.00
CONT_ASSIGN62311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
159 1 1
173 1 1
267 1 1
281 1 1
433 1 1
473 1 1
479 1 1
480 1 1
481 1 1
482 1 1
483 1 1
484 1 1
485 1 1
486 1 1
487 1 1
488 1 1
489 1 1
492 1 1
496 1 1
510 1 1
512 1 1
513 1 1
515 1 1
516 1 1
518 1 1
519 1 1
521 1 1
522 1 1
524 1 1
525 1 1
527 1 1
529 1 1
530 1 1
532 1 1
533 1 1
535 1 1
536 1 1
538 1 1
539 1 1
541 1 1
545 1 1
546 1 1
547 1 1
548 1 1
549 1 1
550 1 1
551 1 1
552 1 1
553 1 1
554 1 1
555 1 1
560 1 1
561 1 1
563 1 1
567 1 1
571 1 1
575 1 1
579 1 1
583 1 1
584 1 1
588 1 1
592 1 1
596 1 1
600 1 1
614 unreachable
622 1 1
623 1 1


Cond Coverage for Module : rv_timer_reg_top
TotalCoveredPercent
Conditions123123100.00
Logical123123100.00
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T12,T13
11CoveredT1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T15,T16
10CoveredT28,T29,T30

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT14,T15,T16
010CoveredT28,T29,T30
100CoveredT14,T15,T16

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT28,T29,T30
010CoveredT4,T12,T13
100CoveredT4,T12,T13

 LINE       480
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_ALERT_TEST_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       481
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_CTRL_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       482
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_INTR_ENABLE0_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       483
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_INTR_STATE0_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       484
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_INTR_TEST0_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       485
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_CFG0_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       486
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_TIMER_V_LOWER0_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       487
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_TIMER_V_UPPER0_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       488
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_COMPARE_LOWER0_0_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       489
 EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_COMPARE_UPPER0_0_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       492
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       492
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       496
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T12,T13

 LINE       496
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))))
-1--2--3--4--5--6--7--8--9--10-StatusTests
0000000000CoveredT1,T2,T3
0000000001CoveredT1,T4,T5
0000000010CoveredT1,T4,T5
0000000100CoveredT1,T3,T4
0000001000CoveredT1,T3,T4
0000010000CoveredT1,T4,T5
0000100000CoveredT1,T4,T5
0001000000CoveredT1,T2,T3
0010000000CoveredT1,T4,T5
0100000000CoveredT1,T4,T5
1000000000CoveredT1,T4,T5

 LINE       496
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       496
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T4,T5

 LINE       496
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T4,T5

 LINE       496
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       496
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       496
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T4,T5

 LINE       496
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T3,T4

 LINE       496
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T3,T4

 LINE       496
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T4,T5

 LINE       496
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T4,T5

 LINE       510
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T4,T5
110CoveredT4,T12,T13
111CoveredT31,T32,T33

 LINE       513
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT4,T12,T13
111CoveredT1,T2,T3

 LINE       516
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT4,T12,T13
111CoveredT1,T2,T3

 LINE       519
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT4,T12,T13
111CoveredT1,T2,T3

 LINE       522
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T4,T5
110CoveredT4,T12,T13
111CoveredT4,T12,T34

 LINE       525
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT4,T12,T13
111CoveredT1,T2,T3

 LINE       530
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT4,T12,T13
111CoveredT1,T2,T3

 LINE       533
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT4,T12,T13
111CoveredT1,T2,T3

 LINE       536
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT4,T12,T13
111CoveredT1,T2,T3

 LINE       539
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT4,T12,T13
111CoveredT1,T2,T3

Branch Coverage for Module : rv_timer_reg_top
Line No.TotalCoveredPercent
Branches 16 16 100.00
TERNARY 492 2 2 100.00
IF 68 3 3 100.00
CASE 561 11 11 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 492 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T14,T15,T16
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 561 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : rv_timer_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 2147483647 131853616 0 0
reAfterRv 2147483647 131853608 0 0
rePulse 2147483647 131768495 0 0
wePulse 2147483647 85113 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 131853616 0 0
T1 117728 668495 0 0
T2 292638 8951 0 0
T3 334451 68366 0 0
T4 124432 7446 0 0
T5 142300 28251 0 0
T6 188100 902836 0 0
T7 175933 459183 0 0
T8 118348 35977 0 0
T9 116552 24423 0 0
T10 154054 113395 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 131853608 0 0
T1 117728 668495 0 0
T2 292638 8951 0 0
T3 334451 68366 0 0
T4 124432 7446 0 0
T5 142300 28251 0 0
T6 188100 902836 0 0
T7 175933 459183 0 0
T8 118348 35977 0 0
T9 116552 24423 0 0
T10 154054 113395 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 131768495 0 0
T1 117728 668458 0 0
T2 292638 8921 0 0
T3 334451 68279 0 0
T4 124432 6417 0 0
T5 142300 28205 0 0
T6 188100 902774 0 0
T7 175933 459133 0 0
T8 118348 35947 0 0
T9 116552 24355 0 0
T10 154054 113389 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 85113 0 0
T1 117728 37 0 0
T2 292638 30 0 0
T3 334451 87 0 0
T4 124432 1029 0 0
T5 142300 46 0 0
T6 188100 62 0 0
T7 175933 50 0 0
T8 118348 30 0 0
T9 116552 68 0 0
T10 154054 61 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%