Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1515852	0	0
cfg0_rd_A	2147483647	2718	0	0
compare_lower0_0_rd_A	2147483647	2771	0	0
compare_upper0_0_rd_A	2147483647	2502	0	0
ctrl_rd_A	2147483647	2646	0	0
intr_enable0_rd_A	2147483647	3738	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1515852	0	0
T4	124432	30905	0	0
T5	142300	0	0	0
T6	188100	0	0	0
T7	175933	0	0	0
T8	118348	0	0	0
T9	116552	0	0	0
T10	154054	0	0	0
T12	0	37392	0	0
T13	0	91242	0	0
T35	0	50311	0	0
T36	0	626578	0	0
T37	0	163943	0	0
T38	0	124282	0	0
T39	0	59941	0	0
T40	0	38250	0	0
T41	0	88655	0	0
T42	343787	0	0	0
T43	337041	0	0	0
T44	148048	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2718	0	0
T4	124432	341	0	0
T5	142300	0	0	0
T6	188100	0	0	0
T7	175933	0	0	0
T8	118348	0	0	0
T9	116552	0	0	0
T10	154054	0	0	0
T30	0	43	0	0
T40	0	174	0	0
T42	343787	0	0	0
T43	337041	0	0	0
T44	148048	0	0	0
T45	0	8	0	0
T46	0	38	0	0
T47	0	39	0	0
T48	0	77	0	0
T49	0	13	0	0
T50	0	37	0	0
T51	0	19	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2771	0	0
T4	124432	430	0	0
T5	142300	0	0	0
T6	188100	0	0	0
T7	175933	0	0	0
T8	118348	0	0	0
T9	116552	0	0	0
T10	154054	0	0	0
T30	0	19	0	0
T40	0	366	0	0
T42	343787	0	0	0
T43	337041	0	0	0
T44	148048	0	0	0
T46	0	57	0	0
T47	0	26	0	0
T48	0	82	0	0
T49	0	8	0	0
T50	0	23	0	0
T51	0	15	0	0
T52	0	28	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2502	0	0
T4	124432	285	0	0
T5	142300	0	0	0
T6	188100	0	0	0
T7	175933	0	0	0
T8	118348	0	0	0
T9	116552	0	0	0
T10	154054	0	0	0
T30	0	43	0	0
T40	0	235	0	0
T42	343787	0	0	0
T43	337041	0	0	0
T44	148048	0	0	0
T45	0	8	0	0
T46	0	37	0	0
T47	0	44	0	0
T48	0	58	0	0
T49	0	40	0	0
T50	0	20	0	0
T53	0	4	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2646	0	0
T4	124432	356	0	0
T5	142300	0	0	0
T6	188100	0	0	0
T7	175933	0	0	0
T8	118348	0	0	0
T9	116552	0	0	0
T10	154054	0	0	0
T30	0	39	0	0
T40	0	249	0	0
T42	343787	0	0	0
T43	337041	0	0	0
T44	148048	0	0	0
T45	0	4	0	0
T46	0	45	0	0
T47	0	24	0	0
T48	0	49	0	0
T49	0	38	0	0
T50	0	17	0	0
T53	0	7	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3738	0	0
T4	124432	432	0	0
T5	142300	0	0	0
T6	188100	0	0	0
T7	175933	0	0	0
T8	118348	0	0	0
T9	116552	0	0	0
T10	154054	0	0	0
T42	343787	0	0	0
T43	337041	0	0	0
T44	148048	0	0	0
T54	0	31	0	0
T55	0	158	0	0
T56	0	41	0	0
T57	0	80	0	0
T58	0	60	0	0
T59	0	37	0	0
T60	0	68	0	0
T61	0	23	0	0
T62	0	29	0	0