Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	63143226	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	65133477	1		T1	10542		T2	269379		T3	2928

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	126568505	1		T1	21107		T2	537803		T3	5822
values[0x0]	811799	1		T1	6		T2	29		T3	37
values[0x1]	896399	1		T1	3		T2	30		T3	24

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	50407467	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	77869236	1		T1	12622		T2	323511		T3	3467

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	329293	1		T2	2099		T3	20		T4	13
valid_sources[0x01]	326570	1		T2	2047		T3	13		T4	5
valid_sources[0x02]	323225	1		T2	2164		T3	11		T4	6
valid_sources[0x03]	327823	1		T2	2077		T3	14		T4	3
valid_sources[0x04]	388407	1		T2	1967		T3	27		T4	8
valid_sources[0x05]	434678	1		T1	21116		T2	2073		T3	14
valid_sources[0x06]	328566	1		T2	2384		T3	30		T4	3
valid_sources[0x07]	326213	1		T2	2155		T3	40		T4	12
valid_sources[0x08]	324217	1		T2	2052		T3	10		T4	12
valid_sources[0x09]	329341	1		T2	2090		T3	27		T4	9
valid_sources[0x0a]	325315	1		T2	2076		T3	32		T4	7
valid_sources[0x0b]	328548	1		T2	2113		T3	21		T4	4
valid_sources[0x0c]	329074	1		T2	2212		T3	21		T4	5
valid_sources[0x0d]	326713	1		T2	2068		T3	20		T4	2
valid_sources[0x0e]	324639	1		T2	2185		T3	28		T4	7
valid_sources[0x0f]	329472	1		T2	1985		T3	38		T4	6
valid_sources[0x10]	323525	1		T2	2094		T3	9		T4	6
valid_sources[0x11]	324692	1		T2	2174		T3	20		T4	3
valid_sources[0x12]	1920883	1		T2	2049		T3	17		T4	10
valid_sources[0x13]	324637	1		T2	2040		T3	35		T4	5
valid_sources[0x14]	1654605	1		T2	2089		T3	20		T4	3
valid_sources[0x15]	327743	1		T2	2048		T3	29		T4	6
valid_sources[0x16]	326635	1		T2	2084		T3	28		T4	5
valid_sources[0x17]	1694458	1		T2	2102		T3	22		T4	3
valid_sources[0x18]	333734	1		T2	2055		T3	27		T4	6
valid_sources[0x19]	326955	1		T2	2308		T3	13		T4	7
valid_sources[0x1a]	326720	1		T2	2173		T3	13		T4	10
valid_sources[0x1b]	374335	1		T2	2067		T3	11		T4	7
valid_sources[0x1c]	325123	1		T2	2183		T3	28		T4	5
valid_sources[0x1d]	324101	1		T2	2112		T3	18		T4	7
valid_sources[0x1e]	323422	1		T2	1999		T3	29		T4	11
valid_sources[0x1f]	325932	1		T2	2220		T3	25		T4	7
valid_sources[0x20]	2194135	1		T2	2024		T3	19		T4	9
valid_sources[0x21]	325286	1		T2	2019		T3	19		T4	6
valid_sources[0x22]	327504	1		T2	2066		T3	43		T4	9
valid_sources[0x23]	721953	1		T2	2114		T3	17		T4	6
valid_sources[0x24]	328895	1		T2	2032		T3	24		T4	8
valid_sources[0x25]	327857	1		T2	2132		T3	14		T4	7
valid_sources[0x26]	325494	1		T2	2060		T3	20		T4	4
valid_sources[0x27]	341611	1		T2	2066		T3	26		T4	8
valid_sources[0x28]	384042	1		T2	2083		T3	26		T4	9
valid_sources[0x29]	839800	1		T2	2180		T3	13		T4	12
valid_sources[0x2a]	1331382	1		T2	2090		T3	11		T4	9
valid_sources[0x2b]	335829	1		T2	2111		T3	19		T4	5
valid_sources[0x2c]	326147	1		T2	2120		T3	14		T4	6
valid_sources[0x2d]	327536	1		T2	2129		T3	17		T4	3
valid_sources[0x2e]	1641901	1		T2	2031		T3	16		T4	6
valid_sources[0x2f]	323652	1		T2	2087		T3	33		T4	4
valid_sources[0x30]	329175	1		T2	2093		T3	24		T4	7
valid_sources[0x31]	1014988	1		T2	2196		T3	33		T4	6
valid_sources[0x32]	324731	1		T2	2231		T3	36		T4	4
valid_sources[0x33]	325113	1		T2	2101		T3	19		T4	3
valid_sources[0x34]	328207	1		T2	2096		T3	19		T4	8
valid_sources[0x35]	326676	1		T2	2071		T3	20		T4	10
valid_sources[0x36]	325771	1		T2	2112		T3	17		T4	6
valid_sources[0x37]	328398	1		T2	2133		T3	14		T4	14
valid_sources[0x38]	324700	1		T2	2022		T3	46		T4	6
valid_sources[0x39]	826452	1		T2	1995		T3	21		T4	2
valid_sources[0x3a]	336143	1		T2	2096		T3	6		T4	5
valid_sources[0x3b]	1757023	1		T2	2120		T3	6		T4	3
valid_sources[0x3c]	355603	1		T2	2143		T3	23		T4	10
valid_sources[0x3d]	350109	1		T2	1914		T3	23		T4	9
valid_sources[0x3e]	342861	1		T2	2134		T3	17		T4	8
valid_sources[0x3f]	341041	1		T2	2155		T3	21		T4	7
valid_sources[0x40]	325643	1		T2	2130		T3	24		T4	6
valid_sources[0x41]	326658	1		T2	2230		T3	41		T4	4
valid_sources[0x42]	326238	1		T2	2078		T3	32		T4	9
valid_sources[0x43]	326401	1		T2	2148		T3	8		T4	5
valid_sources[0x44]	324747	1		T2	2094		T3	33		T4	5
valid_sources[0x45]	328200	1		T2	2005		T3	16		T4	4
valid_sources[0x46]	882270	1		T2	2205		T3	19		T4	10
valid_sources[0x47]	326642	1		T2	2118		T3	31		T4	6
valid_sources[0x48]	328606	1		T2	2130		T3	36		T4	4
valid_sources[0x49]	325922	1		T2	1993		T3	27		T4	7
valid_sources[0x4a]	329288	1		T2	2081		T3	13		T4	14
valid_sources[0x4b]	326239	1		T2	2049		T3	11		T4	6
valid_sources[0x4c]	328586	1		T2	2187		T3	18		T4	2
valid_sources[0x4d]	324872	1		T2	2119		T3	22		T4	8
valid_sources[0x4e]	328963	1		T2	2100		T3	38		T4	3
valid_sources[0x4f]	325207	1		T2	2046		T3	21		T4	5
valid_sources[0x50]	326765	1		T2	2072		T3	38		T4	4
valid_sources[0x51]	498013	1		T2	2152		T3	27		T4	7
valid_sources[0x52]	326999	1		T2	2117		T3	14		T4	1
valid_sources[0x53]	397320	1		T2	2073		T3	26		T4	3
valid_sources[0x54]	329674	1		T2	2164		T3	24		T4	8
valid_sources[0x55]	327629	1		T2	2161		T3	39		T4	7
valid_sources[0x56]	325088	1		T2	2079		T3	28		T4	12
valid_sources[0x57]	327638	1		T2	2200		T3	25		T4	3
valid_sources[0x58]	1770694	1		T2	2056		T3	32		T4	9
valid_sources[0x59]	325089	1		T2	2165		T3	21		T4	3
valid_sources[0x5a]	331355	1		T2	2020		T3	25		T4	8
valid_sources[0x5b]	368215	1		T2	2069		T3	23		T4	8
valid_sources[0x5c]	5923480	1		T2	2129		T3	13		T4	4
valid_sources[0x5d]	341448	1		T2	2026		T3	16		T4	6
valid_sources[0x5e]	326567	1		T2	2207		T3	11		T4	7
valid_sources[0x5f]	326453	1		T2	2172		T3	37		T4	5
valid_sources[0x60]	330918	1		T2	2043		T3	41		T4	5
valid_sources[0x61]	1040724	1		T2	2092		T3	23		T4	7
valid_sources[0x62]	338141	1		T2	2231		T3	37		T4	5
valid_sources[0x63]	985203	1		T2	1946		T3	24		T4	4
valid_sources[0x64]	364358	1		T2	1962		T3	30		T4	8
valid_sources[0x65]	331681	1		T2	2082		T3	19		T4	9
valid_sources[0x66]	325860	1		T2	2087		T3	18		T4	6
valid_sources[0x67]	360613	1		T2	2115		T3	27		T4	7
valid_sources[0x68]	327705	1		T2	1973		T3	28		T4	5
valid_sources[0x69]	327114	1		T2	2145		T3	6		T4	11
valid_sources[0x6a]	324343	1		T2	2033		T3	24		T4	1
valid_sources[0x6b]	327380	1		T2	2085		T3	19		T4	4
valid_sources[0x6c]	327498	1		T2	2135		T3	15		T4	9
valid_sources[0x6d]	326994	1		T2	2082		T3	25		T4	2
valid_sources[0x6e]	328539	1		T2	1952		T3	17		T4	4
valid_sources[0x6f]	325557	1		T2	2127		T3	22		T4	7
valid_sources[0x70]	325294	1		T2	2095		T3	25		T4	6
valid_sources[0x71]	326357	1		T2	2123		T3	25		T4	5
valid_sources[0x72]	328056	1		T2	2108		T3	20		T4	2
valid_sources[0x73]	381812	1		T2	2196		T3	12		T4	9
valid_sources[0x74]	326059	1		T2	2025		T3	30		T4	5
valid_sources[0x75]	326756	1		T2	2138		T3	27		T4	10
valid_sources[0x76]	327214	1		T2	2075		T3	19		T4	4
valid_sources[0x77]	665253	1		T2	2251		T3	23		T4	5
valid_sources[0x78]	348881	1		T2	2029		T3	27		T4	6
valid_sources[0x79]	329117	1		T2	2193		T3	20		T4	3
valid_sources[0x7a]	325123	1		T2	2026		T3	9		T4	11
valid_sources[0x7b]	325141	1		T2	2077		T3	9		T4	9
valid_sources[0x7c]	325429	1		T2	1982		T3	19		T4	5
valid_sources[0x7d]	327495	1		T2	2077		T3	24		T4	5
valid_sources[0x7e]	331149	1		T2	2171		T3	23		T4	9
valid_sources[0x7f]	510620	1		T2	2092		T3	24		T4	4
valid_sources[0x80]	325568	1		T2	2128		T3	33		T4	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63538969

1

T1

10535

T2

269331

T3

2877

values[0x0]

all_enables

biggest_size

798374

1

T1

5

T2

24

T3

36

values[0x1]

all_enables

biggest_size

796134

1

T1

2

T2

24

T3

15