Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2800236	0	0
cfg0_rd_A	2147483647	8585	0	0
compare_lower0_0_rd_A	2147483647	10080	0	0
compare_upper0_0_rd_A	2147483647	8792	0	0
ctrl_rd_A	2147483647	8559	0	0
intr_enable0_rd_A	2147483647	10404	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2800236	0	0
T12	464020	142251	0	0
T13	0	88504	0	0
T14	0	157550	0	0
T24	0	607585	0	0
T34	240822	0	0	0
T36	0	173944	0	0
T37	0	27829	0	0
T38	0	150421	0	0
T39	0	105860	0	0
T40	0	184883	0	0
T41	0	50449	0	0
T42	802951	0	0	0
T43	282700	0	0	0
T44	157646	0	0	0
T45	284730	0	0	0
T46	735765	0	0	0
T47	357027	0	0	0
T48	202042	0	0	0
T49	506596	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8585	0	0
T13	426519	845	0	0
T33	0	5	0	0
T36	0	911	0	0
T38	0	1243	0	0
T50	0	1241	0	0
T51	0	943	0	0
T52	0	225	0	0
T53	0	1546	0	0
T54	0	85	0	0
T55	0	20	0	0
T56	863923	0	0	0
T57	463311	0	0	0
T58	173481	0	0	0
T59	437488	0	0	0
T60	127209	0	0	0
T61	482487	0	0	0
T62	419503	0	0	0
T63	182556	0	0	0
T64	138432	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10080	0	0
T13	426519	918	0	0
T33	0	3	0	0
T36	0	1337	0	0
T38	0	1738	0	0
T50	0	1641	0	0
T51	0	864	0	0
T52	0	320	0	0
T53	0	1804	0	0
T54	0	59	0	0
T55	0	27	0	0
T56	863923	0	0	0
T57	463311	0	0	0
T58	173481	0	0	0
T59	437488	0	0	0
T60	127209	0	0	0
T61	482487	0	0	0
T62	419503	0	0	0
T63	182556	0	0	0
T64	138432	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8792	0	0
T13	426519	990	0	0
T33	0	2	0	0
T36	0	888	0	0
T38	0	1612	0	0
T50	0	1294	0	0
T51	0	761	0	0
T52	0	216	0	0
T53	0	1586	0	0
T54	0	73	0	0
T55	0	27	0	0
T56	863923	0	0	0
T57	463311	0	0	0
T58	173481	0	0	0
T59	437488	0	0	0
T60	127209	0	0	0
T61	482487	0	0	0
T62	419503	0	0	0
T63	182556	0	0	0
T64	138432	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8559	0	0
T13	426519	827	0	0
T33	0	4	0	0
T36	0	953	0	0
T38	0	1508	0	0
T50	0	1385	0	0
T51	0	789	0	0
T52	0	235	0	0
T53	0	1432	0	0
T54	0	39	0	0
T55	0	13	0	0
T56	863923	0	0	0
T57	463311	0	0	0
T58	173481	0	0	0
T59	437488	0	0	0
T60	127209	0	0	0
T61	482487	0	0	0
T62	419503	0	0	0
T63	182556	0	0	0
T64	138432	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10404	0	0
T13	426519	1061	0	0
T36	0	1182	0	0
T38	0	1808	0	0
T56	863923	0	0	0
T57	463311	0	0	0
T58	173481	0	0	0
T59	437488	0	0	0
T65	476869	45	0	0
T66	0	11	0	0
T67	0	50	0	0
T68	0	31	0	0
T69	0	21	0	0
T70	0	49	0	0
T71	0	94	0	0
T72	630647	0	0	0
T73	590196	0	0	0
T74	340371	0	0	0
T75	549343	0	0	0