Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1032783	0	0
cfg0_rd_A	2147483647	3938	0	0
compare_lower0_0_rd_A	2147483647	4088	0	0
compare_upper0_0_rd_A	2147483647	3700	0	0
ctrl_rd_A	2147483647	3499	0	0
intr_enable0_rd_A	2147483647	5263	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1032783	0	0
T3	258330	69007	0	0
T4	118382	0	0	0
T5	536138	0	0	0
T6	491479	0	0	0
T7	180370	0	0	0
T8	958989	0	0	0
T9	658542	0	0	0
T10	194246	0	0	0
T11	0	84428	0	0
T12	0	326232	0	0
T33	0	56407	0	0
T34	0	161755	0	0
T35	0	63195	0	0
T36	0	154919	0	0
T37	0	26263	0	0
T38	0	76519	0	0
T39	0	1109	0	0
T40	237946	0	0	0
T41	331443	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3938	0	0
T3	258330	395	0	0
T4	118382	0	0	0
T5	536138	0	0	0
T6	491479	0	0	0
T7	180370	0	0	0
T8	958989	0	0	0
T9	658542	0	0	0
T10	194246	0	0	0
T11	0	917	0	0
T30	0	10	0	0
T31	0	12	0	0
T32	0	54	0	0
T37	0	340	0	0
T38	0	384	0	0
T40	237946	0	0	0
T41	331443	0	0	0
T42	0	35	0	0
T43	0	1	0	0
T44	0	5	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4088	0	0
T3	258330	370	0	0
T4	118382	0	0	0
T5	536138	0	0	0
T6	491479	0	0	0
T7	180370	0	0	0
T8	958989	0	0	0
T9	658542	0	0	0
T10	194246	0	0	0
T11	0	1113	0	0
T30	0	8	0	0
T31	0	2	0	0
T32	0	97	0	0
T37	0	307	0	0
T38	0	467	0	0
T40	237946	0	0	0
T41	331443	0	0	0
T42	0	8	0	0
T43	0	6	0	0
T44	0	2	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3700	0	0
T3	258330	300	0	0
T4	118382	0	0	0
T5	536138	0	0	0
T6	491479	0	0	0
T7	180370	0	0	0
T8	958989	0	0	0
T9	658542	0	0	0
T10	194246	0	0	0
T11	0	839	0	0
T31	0	8	0	0
T32	0	88	0	0
T37	0	276	0	0
T38	0	517	0	0
T40	237946	0	0	0
T41	331443	0	0	0
T42	0	8	0	0
T43	0	6	0	0
T44	0	5	0	0
T45	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3499	0	0
T3	258330	336	0	0
T4	118382	0	0	0
T5	536138	0	0	0
T6	491479	0	0	0
T7	180370	0	0	0
T8	958989	0	0	0
T9	658542	0	0	0
T10	194246	0	0	0
T11	0	847	0	0
T30	0	4	0	0
T31	0	5	0	0
T32	0	33	0	0
T37	0	248	0	0
T38	0	354	0	0
T40	237946	0	0	0
T41	331443	0	0	0
T42	0	12	0	0
T43	0	4	0	0
T46	0	21	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5263	0	0
T1	445118	61	0	0
T2	140987	0	0	0
T3	258330	519	0	0
T4	118382	0	0	0
T5	536138	0	0	0
T6	491479	0	0	0
T7	180370	0	0	0
T8	958989	0	0	0
T9	658542	0	0	0
T10	194246	0	0	0
T11	0	1254	0	0
T47	0	55	0	0
T48	0	26	0	0
T49	0	130	0	0
T50	0	40	0	0
T51	0	86	0	0
T52	0	11	0	0
T53	0	18	0	0