Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58373910	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	60694909	1		T1	4677		T2	674498		T3	88740

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	117089007	1		T1	9362		T2	134779		T3	177253
values[0x0]	941126	1		T1	8		T2	25		T3	22
values[0x1]	1038686	1		T1	3		T2	28		T3	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46594679	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	72474140	1		T1	5625		T2	809681		T3	106484

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	351406	1		T1	46		T2	5145		T3	734
valid_sources[0x01]	349111	1		T1	43		T2	5216		T3	640
valid_sources[0x02]	346029	1		T1	25		T2	5134		T3	765
valid_sources[0x03]	808418	1		T1	36		T2	5328		T3	682
valid_sources[0x04]	457715	1		T1	36		T2	5148		T3	694
valid_sources[0x05]	348183	1		T1	30		T2	5273		T3	680
valid_sources[0x06]	350705	1		T1	42		T2	5121		T3	785
valid_sources[0x07]	436161	1		T1	33		T2	5355		T3	639
valid_sources[0x08]	355240	1		T1	27		T2	5273		T3	715
valid_sources[0x09]	347978	1		T1	32		T2	5287		T3	730
valid_sources[0x0a]	348453	1		T1	34		T2	5236		T3	673
valid_sources[0x0b]	346829	1		T1	33		T2	5278		T3	637
valid_sources[0x0c]	349171	1		T1	34		T2	5295		T3	632
valid_sources[0x0d]	351735	1		T1	39		T2	5364		T3	661
valid_sources[0x0e]	350738	1		T1	37		T2	5311		T3	690
valid_sources[0x0f]	397365	1		T1	44		T2	5278		T3	707
valid_sources[0x10]	349287	1		T1	34		T2	5208		T3	719
valid_sources[0x11]	350488	1		T1	40		T2	5236		T3	674
valid_sources[0x12]	347700	1		T1	42		T2	5245		T3	723
valid_sources[0x13]	906657	1		T1	25		T2	5240		T3	654
valid_sources[0x14]	347715	1		T1	27		T2	5292		T3	635
valid_sources[0x15]	707846	1		T1	41		T2	5247		T3	684
valid_sources[0x16]	404000	1		T1	41		T2	5254		T3	618
valid_sources[0x17]	348571	1		T1	31		T2	5206		T3	757
valid_sources[0x18]	348952	1		T1	35		T2	5344		T3	696
valid_sources[0x19]	4614158	1		T1	50		T2	5247		T3	668
valid_sources[0x1a]	350478	1		T1	30		T2	5378		T3	702
valid_sources[0x1b]	442353	1		T1	30		T2	5417		T3	628
valid_sources[0x1c]	346918	1		T1	37		T2	5111		T3	666
valid_sources[0x1d]	729983	1		T1	36		T2	5376		T3	771
valid_sources[0x1e]	351718	1		T1	39		T2	5382		T3	633
valid_sources[0x1f]	348104	1		T1	50		T2	5331		T3	670
valid_sources[0x20]	345807	1		T1	43		T2	5120		T3	633
valid_sources[0x21]	349963	1		T1	45		T2	5226		T3	621
valid_sources[0x22]	352678	1		T1	35		T2	5165		T3	661
valid_sources[0x23]	352194	1		T1	43		T2	5330		T3	626
valid_sources[0x24]	347195	1		T1	39		T2	5249		T3	711
valid_sources[0x25]	357578	1		T1	34		T2	5303		T3	638
valid_sources[0x26]	366423	1		T1	36		T2	5244		T3	748
valid_sources[0x27]	346486	1		T1	48		T2	5420		T3	673
valid_sources[0x28]	694816	1		T1	34		T2	5171		T3	752
valid_sources[0x29]	347282	1		T1	38		T2	5358		T3	689
valid_sources[0x2a]	347315	1		T1	30		T2	5291		T3	690
valid_sources[0x2b]	347900	1		T1	42		T2	5265		T3	750
valid_sources[0x2c]	401086	1		T1	34		T2	5366		T3	708
valid_sources[0x2d]	665927	1		T1	21		T2	5269		T3	729
valid_sources[0x2e]	349817	1		T1	43		T2	5321		T3	718
valid_sources[0x2f]	363741	1		T1	33		T2	5258		T3	682
valid_sources[0x30]	348345	1		T1	44		T2	5103		T3	730
valid_sources[0x31]	349843	1		T1	58		T2	5300		T3	685
valid_sources[0x32]	347296	1		T1	42		T2	5375		T3	655
valid_sources[0x33]	363031	1		T1	31		T2	5429		T3	741
valid_sources[0x34]	348161	1		T1	26		T2	5224		T3	707
valid_sources[0x35]	350770	1		T1	27		T2	5202		T3	802
valid_sources[0x36]	346775	1		T1	42		T2	5245		T3	708
valid_sources[0x37]	347856	1		T1	36		T2	5328		T3	676
valid_sources[0x38]	346091	1		T1	31		T2	5247		T3	668
valid_sources[0x39]	348487	1		T1	36		T2	5230		T3	692
valid_sources[0x3a]	349079	1		T1	46		T2	5300		T3	718
valid_sources[0x3b]	522527	1		T1	36		T2	5164		T3	735
valid_sources[0x3c]	346541	1		T1	41		T2	5186		T3	684
valid_sources[0x3d]	347327	1		T1	28		T2	5264		T3	760
valid_sources[0x3e]	368866	1		T1	57		T2	5219		T3	682
valid_sources[0x3f]	346430	1		T1	42		T2	5182		T3	676
valid_sources[0x40]	352978	1		T1	43		T2	5341		T3	702
valid_sources[0x41]	1195823	1		T1	42		T2	5233		T3	668
valid_sources[0x42]	348914	1		T1	38		T2	5311		T3	709
valid_sources[0x43]	347934	1		T1	35		T2	5426		T3	615
valid_sources[0x44]	347657	1		T1	32		T2	5190		T3	669
valid_sources[0x45]	351316	1		T1	45		T2	5306		T3	684
valid_sources[0x46]	347744	1		T1	41		T2	5316		T3	810
valid_sources[0x47]	811100	1		T1	43		T2	5286		T3	666
valid_sources[0x48]	371639	1		T1	49		T2	5306		T3	592
valid_sources[0x49]	802793	1		T1	46		T2	5163		T3	698
valid_sources[0x4a]	347899	1		T1	34		T2	5316		T3	648
valid_sources[0x4b]	350889	1		T1	40		T2	5225		T3	667
valid_sources[0x4c]	348792	1		T1	32		T2	5102		T3	689
valid_sources[0x4d]	347622	1		T1	39		T2	5292		T3	661
valid_sources[0x4e]	349043	1		T1	42		T2	5281		T3	693
valid_sources[0x4f]	346700	1		T1	32		T2	5376		T3	797
valid_sources[0x50]	809122	1		T1	41		T2	5216		T3	634
valid_sources[0x51]	347635	1		T1	36		T2	5250		T3	695
valid_sources[0x52]	348516	1		T1	21		T2	5279		T3	645
valid_sources[0x53]	345598	1		T1	48		T2	5189		T3	693
valid_sources[0x54]	379168	1		T1	35		T2	5235		T3	605
valid_sources[0x55]	345911	1		T1	43		T2	5297		T3	779
valid_sources[0x56]	488715	1		T1	33		T2	5389		T3	756
valid_sources[0x57]	347032	1		T1	26		T2	5223		T3	664
valid_sources[0x58]	348688	1		T1	50		T2	5278		T3	725
valid_sources[0x59]	348137	1		T1	37		T2	5309		T3	692
valid_sources[0x5a]	348111	1		T1	32		T2	5213		T3	694
valid_sources[0x5b]	349245	1		T1	36		T2	5249		T3	625
valid_sources[0x5c]	351060	1		T1	24		T2	5270		T3	739
valid_sources[0x5d]	350620	1		T1	43		T2	5313		T3	592
valid_sources[0x5e]	1372811	1		T1	31		T2	5300		T3	651
valid_sources[0x5f]	351080	1		T1	31		T2	5190		T3	751
valid_sources[0x60]	347874	1		T1	39		T2	5131		T3	650
valid_sources[0x61]	468709	1		T1	41		T2	5365		T3	674
valid_sources[0x62]	346691	1		T1	32		T2	5391		T3	694
valid_sources[0x63]	349272	1		T1	27		T2	5245		T3	700
valid_sources[0x64]	364534	1		T1	40		T2	5173		T3	628
valid_sources[0x65]	344991	1		T1	40		T2	5123		T3	686
valid_sources[0x66]	347132	1		T1	31		T2	5290		T3	837
valid_sources[0x67]	347015	1		T1	34		T2	5164		T3	654
valid_sources[0x68]	349029	1		T1	34		T2	5285		T3	705
valid_sources[0x69]	347844	1		T1	35		T2	5254		T3	722
valid_sources[0x6a]	413331	1		T1	39		T2	5347		T3	760
valid_sources[0x6b]	505360	1		T1	31		T2	5283		T3	693
valid_sources[0x6c]	349326	1		T1	34		T2	5392		T3	636
valid_sources[0x6d]	349036	1		T1	29		T2	5265		T3	669
valid_sources[0x6e]	348306	1		T1	30		T2	5212		T3	672
valid_sources[0x6f]	347347	1		T1	47		T2	5154		T3	704
valid_sources[0x70]	348453	1		T1	33		T2	5254		T3	671
valid_sources[0x71]	404907	1		T1	42		T2	5273		T3	631
valid_sources[0x72]	350636	1		T1	42		T2	5316		T3	656
valid_sources[0x73]	346026	1		T1	33		T2	5255		T3	680
valid_sources[0x74]	618869	1		T1	52		T2	5259		T3	711
valid_sources[0x75]	345235	1		T1	34		T2	5423		T3	719
valid_sources[0x76]	394126	1		T1	40		T2	5246		T3	697
valid_sources[0x77]	347809	1		T1	33		T2	5398		T3	665
valid_sources[0x78]	348212	1		T1	31		T2	5247		T3	763
valid_sources[0x79]	368767	1		T1	37		T2	5328		T3	613
valid_sources[0x7a]	347727	1		T1	36		T2	5314		T3	723
valid_sources[0x7b]	382339	1		T1	31		T2	5376		T3	652
valid_sources[0x7c]	348715	1		T1	40		T2	5156		T3	640
valid_sources[0x7d]	349138	1		T1	41		T2	5387		T3	668
valid_sources[0x7e]	347376	1		T1	50		T2	5203		T3	731
valid_sources[0x7f]	1791528	1		T1	42		T2	5213		T3	706
valid_sources[0x80]	375420	1		T1	38		T2	5180		T3	704

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

58844170

1

T1

4670

T2

674458

T3

88706

values[0x0]

all_enables

biggest_size

925939

1

T1

6

T2

21

T3

17

values[0x1]

all_enables

biggest_size

924800

1

T1

1

T2

19

T3

17