Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	3226706	0	0
cfg0_rd_A	2147483647	9084	0	0
compare_lower0_0_rd_A	2147483647	9350	0	0
compare_upper0_0_rd_A	2147483647	8601	0	0
ctrl_rd_A	2147483647	8540	0	0
intr_enable0_rd_A	2147483647	10721	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3226706	0	0
T11	120325	274162	0	0
T12	0	173236	0	0
T13	0	515784	0	0
T34	0	87211	0	0
T35	0	90204	0	0
T36	0	534559	0	0
T37	0	263210	0	0
T38	0	73255	0	0
T39	0	282128	0	0
T40	0	167680	0	0
T41	136591	0	0	0
T42	439813	0	0	0
T43	637521	0	0	0
T44	449549	0	0	0
T45	117451	0	0	0
T46	126409	0	0	0
T47	803863	0	0	0
T48	148451	0	0	0
T49	106925	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9084	0	0
T11	120325	2617	0	0
T28	0	150	0	0
T31	0	10	0	0
T34	0	857	0	0
T35	0	483	0	0
T37	0	2704	0	0
T38	0	391	0	0
T41	136591	0	0	0
T42	439813	0	0	0
T43	637521	0	0	0
T44	449549	0	0	0
T45	117451	0	0	0
T46	126409	0	0	0
T47	803863	0	0	0
T48	148451	0	0	0
T49	106925	0	0	0
T50	0	22	0	0
T51	0	7	0	0
T52	0	5	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9350	0	0
T11	120325	2871	0	0
T28	0	139	0	0
T31	0	12	0	0
T34	0	938	0	0
T35	0	487	0	0
T37	0	2894	0	0
T38	0	479	0	0
T41	136591	0	0	0
T42	439813	0	0	0
T43	637521	0	0	0
T44	449549	0	0	0
T45	117451	0	0	0
T46	126409	0	0	0
T47	803863	0	0	0
T48	148451	0	0	0
T49	106925	0	0	0
T50	0	17	0	0
T51	0	13	0	0
T52	0	2	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8601	0	0
T11	120325	2445	0	0
T28	0	132	0	0
T31	0	7	0	0
T34	0	904	0	0
T35	0	486	0	0
T37	0	2719	0	0
T38	0	379	0	0
T41	136591	0	0	0
T42	439813	0	0	0
T43	637521	0	0	0
T44	449549	0	0	0
T45	117451	0	0	0
T46	126409	0	0	0
T47	803863	0	0	0
T48	148451	0	0	0
T49	106925	0	0	0
T50	0	29	0	0
T51	0	5	0	0
T52	0	7	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8540	0	0
T11	120325	2874	0	0
T28	0	127	0	0
T31	0	13	0	0
T34	0	839	0	0
T35	0	454	0	0
T37	0	2346	0	0
T38	0	296	0	0
T41	136591	0	0	0
T42	439813	0	0	0
T43	637521	0	0	0
T44	449549	0	0	0
T45	117451	0	0	0
T46	126409	0	0	0
T47	803863	0	0	0
T48	148451	0	0	0
T49	106925	0	0	0
T50	0	20	0	0
T51	0	6	0	0
T52	0	3	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10721	0	0
T11	120325	3104	0	0
T34	0	1080	0	0
T35	0	628	0	0
T37	0	3268	0	0
T41	136591	0	0	0
T42	439813	0	0	0
T43	637521	0	0	0
T44	449549	0	0	0
T45	117451	0	0	0
T46	126409	0	0	0
T47	803863	0	0	0
T48	148451	0	0	0
T49	106925	0	0	0
T53	0	7	0	0
T54	0	5	0	0
T55	0	50	0	0
T56	0	45	0	0
T57	0	32	0	0
T58	0	56	0	0