Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59312758	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	60837924	1		T1	177452		T2	2261		T3	14345

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	118829045	1		T1	353475		T2	4330		T3	29083
values[0x0]	627943	1		T1	29		T2	21		T3	6
values[0x1]	693694	1		T1	21		T2	21		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47361992	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	72788690	1		T1	212820		T2	2689		T3	17295

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	840632	1		T1	1246		T2	14		T3	104
valid_sources[0x01]	323921	1		T1	1412		T2	14		T3	106
valid_sources[0x02]	706075	1		T1	1310		T2	14		T3	109
valid_sources[0x03]	325190	1		T1	1518		T2	16		T3	95
valid_sources[0x04]	480088	1		T1	1406		T2	15		T3	96
valid_sources[0x05]	328585	1		T1	1322		T2	14		T3	132
valid_sources[0x06]	551799	1		T1	1349		T2	15		T3	99
valid_sources[0x07]	326785	1		T1	1409		T2	23		T3	123
valid_sources[0x08]	329530	1		T1	1491		T2	25		T3	108
valid_sources[0x09]	325226	1		T1	1269		T2	9		T3	91
valid_sources[0x0a]	324328	1		T1	1365		T2	13		T3	121
valid_sources[0x0b]	325298	1		T1	1430		T2	10		T3	96
valid_sources[0x0c]	373840	1		T1	1311		T2	9		T3	107
valid_sources[0x0d]	345973	1		T1	1296		T2	9		T3	96
valid_sources[0x0e]	328864	1		T1	1433		T2	13		T3	126
valid_sources[0x0f]	644884	1		T1	1422		T2	11		T3	115
valid_sources[0x10]	326270	1		T1	1292		T2	15		T3	125
valid_sources[0x11]	327222	1		T1	1418		T2	22		T3	126
valid_sources[0x12]	328943	1		T1	1401		T2	20		T3	113
valid_sources[0x13]	328412	1		T1	1425		T2	34		T3	131
valid_sources[0x14]	547283	1		T1	1344		T2	17		T3	100
valid_sources[0x15]	328447	1		T1	1348		T2	14		T3	131
valid_sources[0x16]	325697	1		T1	1336		T2	21		T3	151
valid_sources[0x17]	328142	1		T1	1444		T2	14		T3	101
valid_sources[0x18]	325671	1		T1	1470		T2	15		T3	115
valid_sources[0x19]	356497	1		T1	1410		T2	10		T3	117
valid_sources[0x1a]	326293	1		T1	1416		T2	17		T3	103
valid_sources[0x1b]	326228	1		T1	1376		T2	17		T3	116
valid_sources[0x1c]	326077	1		T1	1460		T2	15		T3	119
valid_sources[0x1d]	323605	1		T1	1360		T2	13		T3	97
valid_sources[0x1e]	326273	1		T1	1443		T2	16		T3	114
valid_sources[0x1f]	327514	1		T1	1306		T2	13		T3	141
valid_sources[0x20]	326110	1		T1	1313		T2	10		T3	100
valid_sources[0x21]	325797	1		T1	1275		T2	14		T3	122
valid_sources[0x22]	331975	1		T1	1428		T2	15		T3	96
valid_sources[0x23]	325411	1		T1	1309		T2	21		T3	112
valid_sources[0x24]	341452	1		T1	1368		T2	19		T3	138
valid_sources[0x25]	325817	1		T1	1364		T2	13		T3	128
valid_sources[0x26]	326182	1		T1	1436		T2	15		T3	115
valid_sources[0x27]	1378402	1		T1	1400		T2	20		T3	129
valid_sources[0x28]	324268	1		T1	1378		T2	6		T3	101
valid_sources[0x29]	325730	1		T1	1428		T2	21		T3	117
valid_sources[0x2a]	955166	1		T1	1456		T2	15		T3	110
valid_sources[0x2b]	328890	1		T1	1312		T2	25		T3	110
valid_sources[0x2c]	327260	1		T1	1338		T2	15		T3	105
valid_sources[0x2d]	326533	1		T1	1343		T2	17		T3	116
valid_sources[0x2e]	326470	1		T1	1390		T2	28		T3	129
valid_sources[0x2f]	325530	1		T1	1365		T2	19		T3	115
valid_sources[0x30]	326550	1		T1	1280		T2	32		T3	104
valid_sources[0x31]	383512	1		T1	1351		T2	9		T3	112
valid_sources[0x32]	329035	1		T1	1528		T2	16		T3	116
valid_sources[0x33]	322457	1		T1	1266		T2	22		T3	103
valid_sources[0x34]	324733	1		T1	1380		T2	10		T3	101
valid_sources[0x35]	328655	1		T1	1344		T2	16		T3	107
valid_sources[0x36]	365444	1		T1	1552		T2	15		T3	138
valid_sources[0x37]	327051	1		T1	1318		T2	13		T3	103
valid_sources[0x38]	325644	1		T1	1374		T2	17		T3	130
valid_sources[0x39]	328184	1		T1	1383		T2	15		T3	107
valid_sources[0x3a]	1108647	1		T1	1428		T2	28		T3	121
valid_sources[0x3b]	324928	1		T1	1301		T2	4		T3	108
valid_sources[0x3c]	327842	1		T1	1403		T2	14		T3	134
valid_sources[0x3d]	665093	1		T1	1322		T2	9		T3	137
valid_sources[0x3e]	907989	1		T1	1420		T2	17		T3	116
valid_sources[0x3f]	327594	1		T1	1347		T2	10		T3	105
valid_sources[0x40]	507134	1		T1	1429		T2	15		T3	116
valid_sources[0x41]	346571	1		T1	1336		T2	17		T3	111
valid_sources[0x42]	3478743	1		T1	1397		T2	15		T3	128
valid_sources[0x43]	326313	1		T1	1417		T2	17		T3	130
valid_sources[0x44]	350615	1		T1	1378		T2	17		T3	115
valid_sources[0x45]	373294	1		T1	1360		T2	17		T3	110
valid_sources[0x46]	327008	1		T1	1408		T2	23		T3	118
valid_sources[0x47]	466188	1		T1	1341		T2	21		T3	98
valid_sources[0x48]	325082	1		T1	1453		T2	31		T3	129
valid_sources[0x49]	373104	1		T1	1345		T2	8		T3	117
valid_sources[0x4a]	328721	1		T1	1447		T2	14		T3	131
valid_sources[0x4b]	327548	1		T1	1490		T2	8		T3	117
valid_sources[0x4c]	324287	1		T1	1454		T2	23		T3	115
valid_sources[0x4d]	325431	1		T1	1423		T2	15		T3	109
valid_sources[0x4e]	326827	1		T1	1387		T2	27		T3	108
valid_sources[0x4f]	325742	1		T1	1448		T2	22		T3	113
valid_sources[0x50]	323709	1		T1	1338		T2	14		T3	112
valid_sources[0x51]	328325	1		T1	1438		T2	18		T3	115
valid_sources[0x52]	324311	1		T1	1309		T2	12		T3	126
valid_sources[0x53]	326874	1		T1	1443		T2	14		T3	107
valid_sources[0x54]	324439	1		T1	1355		T2	11		T3	109
valid_sources[0x55]	326447	1		T1	1413		T2	19		T3	99
valid_sources[0x56]	325806	1		T1	1455		T2	21		T3	104
valid_sources[0x57]	539755	1		T1	1415		T2	23		T3	111
valid_sources[0x58]	327676	1		T1	1320		T2	22		T3	114
valid_sources[0x59]	3297032	1		T1	1311		T2	8		T3	113
valid_sources[0x5a]	333297	1		T1	1368		T2	9		T3	126
valid_sources[0x5b]	325562	1		T1	1320		T2	13		T3	133
valid_sources[0x5c]	326608	1		T1	1334		T2	24		T3	108
valid_sources[0x5d]	346914	1		T1	1345		T2	11		T3	129
valid_sources[0x5e]	1379132	1		T1	1387		T2	25		T3	128
valid_sources[0x5f]	327018	1		T1	1523		T2	14		T3	105
valid_sources[0x60]	330101	1		T1	1505		T2	18		T3	122
valid_sources[0x61]	328003	1		T1	1385		T2	11		T3	96
valid_sources[0x62]	329199	1		T1	1348		T2	23		T3	108
valid_sources[0x63]	327624	1		T1	1440		T2	6		T3	115
valid_sources[0x64]	325278	1		T1	1391		T2	19		T3	114
valid_sources[0x65]	337519	1		T1	1417		T2	14		T3	122
valid_sources[0x66]	325631	1		T1	1390		T2	13		T3	93
valid_sources[0x67]	328073	1		T1	1328		T2	21		T3	92
valid_sources[0x68]	327703	1		T1	1280		T2	8		T3	130
valid_sources[0x69]	961985	1		T1	1332		T2	20		T3	99
valid_sources[0x6a]	326827	1		T1	1348		T2	16		T3	123
valid_sources[0x6b]	324932	1		T1	1463		T2	9		T3	111
valid_sources[0x6c]	328287	1		T1	1496		T2	16		T3	116
valid_sources[0x6d]	325781	1		T1	1390		T2	19		T3	114
valid_sources[0x6e]	345947	1		T1	1269		T2	33		T3	110
valid_sources[0x6f]	328260	1		T1	1332		T2	15		T3	129
valid_sources[0x70]	326456	1		T1	1338		T2	17		T3	114
valid_sources[0x71]	328411	1		T1	1355		T2	13		T3	119
valid_sources[0x72]	333273	1		T1	1567		T2	11		T3	102
valid_sources[0x73]	324696	1		T1	1267		T2	6		T3	92
valid_sources[0x74]	844542	1		T1	1447		T2	14		T3	125
valid_sources[0x75]	1039273	1		T1	1324		T2	24		T3	86
valid_sources[0x76]	325845	1		T1	1367		T2	25		T3	121
valid_sources[0x77]	327488	1		T1	1269		T2	13		T3	109
valid_sources[0x78]	325920	1		T1	1376		T2	14		T3	109
valid_sources[0x79]	324526	1		T1	1387		T2	20		T3	109
valid_sources[0x7a]	571594	1		T1	1315		T2	14		T3	94
valid_sources[0x7b]	1507759	1		T1	1383		T2	11		T3	112
valid_sources[0x7c]	321276	1		T1	1422		T2	22		T3	93
valid_sources[0x7d]	926364	1		T1	1340		T2	16		T3	92
valid_sources[0x7e]	471250	1		T1	1391		T2	24		T3	125
valid_sources[0x7f]	326595	1		T1	1408		T2	23		T3	96
valid_sources[0x80]	324268	1		T1	1379		T2	34		T3	119

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

59607735

1

T1

177419

T2

2230

T3

14339

values[0x0]

all_enables

biggest_size

616113

1

T1

21

T2

19

T3

4

values[0x1]

all_enables

biggest_size

614076

1

T1

12

T2

12

T3

2