Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2159429	0	0
cfg0_rd_A	2147483647	2904	0	0
compare_lower0_0_rd_A	2147483647	2699	0	0
compare_upper0_0_rd_A	2147483647	2514	0	0
ctrl_rd_A	2147483647	2512	0	0
intr_enable0_rd_A	2147483647	3799	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2159429	0	0
T14	173126	53007	0	0
T15	0	351375	0	0
T16	0	154332	0	0
T37	0	76163	0	0
T38	0	147253	0	0
T39	0	56276	0	0
T40	0	53752	0	0
T41	0	74574	0	0
T42	0	51265	0	0
T43	0	39180	0	0
T44	884056	0	0	0
T45	264446	0	0	0
T46	215254	0	0	0
T47	14258	0	0	0
T48	659399	0	0	0
T49	273400	0	0	0
T50	100686	0	0	0
T51	353210	0	0	0
T52	640366	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2904	0	0
T31	0	64	0	0
T36	0	50	0	0
T40	210302	604	0	0
T43	0	368	0	0
T53	0	41	0	0
T54	0	14	0	0
T55	0	445	0	0
T56	0	4	0	0
T57	0	1	0	0
T58	0	15	0	0
T59	366464	0	0	0
T60	397745	0	0	0
T61	795372	0	0	0
T62	411364	0	0	0
T63	954042	0	0	0
T64	315901	0	0	0
T65	422074	0	0	0
T66	226673	0	0	0
T67	539898	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2699	0	0
T31	0	41	0	0
T36	0	44	0	0
T40	210302	658	0	0
T43	0	451	0	0
T53	0	51	0	0
T54	0	14	0	0
T55	0	448	0	0
T56	0	14	0	0
T57	0	12	0	0
T58	0	12	0	0
T59	366464	0	0	0
T60	397745	0	0	0
T61	795372	0	0	0
T62	411364	0	0	0
T63	954042	0	0	0
T64	315901	0	0	0
T65	422074	0	0	0
T66	226673	0	0	0
T67	539898	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2514	0	0
T31	0	48	0	0
T33	0	106	0	0
T36	0	37	0	0
T40	210302	537	0	0
T43	0	430	0	0
T53	0	36	0	0
T54	0	3	0	0
T55	0	416	0	0
T56	0	13	0	0
T58	0	23	0	0
T59	366464	0	0	0
T60	397745	0	0	0
T61	795372	0	0	0
T62	411364	0	0	0
T63	954042	0	0	0
T64	315901	0	0	0
T65	422074	0	0	0
T66	226673	0	0	0
T67	539898	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2512	0	0
T31	0	42	0	0
T36	0	40	0	0
T40	210302	544	0	0
T43	0	471	0	0
T53	0	28	0	0
T54	0	7	0	0
T55	0	445	0	0
T56	0	6	0	0
T57	0	4	0	0
T58	0	11	0	0
T59	366464	0	0	0
T60	397745	0	0	0
T61	795372	0	0	0
T62	411364	0	0	0
T63	954042	0	0	0
T64	315901	0	0	0
T65	422074	0	0	0
T66	226673	0	0	0
T67	539898	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3799	0	0
T40	0	721	0	0
T43	0	409	0	0
T68	176919	101	0	0
T69	0	19	0	0
T70	0	68	0	0
T71	0	11	0	0
T72	0	16	0	0
T73	0	59	0	0
T74	0	51	0	0
T75	0	62	0	0
T76	207089	0	0	0
T77	654077	0	0	0
T78	937210	0	0	0
T79	114399	0	0	0
T80	374919	0	0	0
T81	102181	0	0	0
T82	165260	0	0	0
T83	740648	0	0	0
T84	120864	0	0	0