Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2711465	0	0
cfg0_rd_A	2147483647	6872	0	0
compare_lower0_0_rd_A	2147483647	7048	0	0
compare_upper0_0_rd_A	2147483647	6116	0	0
ctrl_rd_A	2147483647	6153	0	0
intr_enable0_rd_A	2147483647	8294	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2711465	0	0
T13	422786	179485	0	0
T14	0	117574	0	0
T15	0	95552	0	0
T27	202001	0	0	0
T28	0	113163	0	0
T29	0	61367	0	0
T30	0	115535	0	0
T31	0	272589	0	0
T32	0	60289	0	0
T33	0	344885	0	0
T34	0	78010	0	0
T35	155710	0	0	0
T36	260979	0	0	0
T37	862671	0	0	0
T38	167370	0	0	0
T39	187524	0	0	0
T40	286154	0	0	0
T41	802429	0	0	0
T42	426434	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6872	0	0
T25	0	9	0	0
T28	433892	1132	0	0
T43	0	524	0	0
T44	0	95	0	0
T45	0	1150	0	0
T46	0	2273	0	0
T47	0	10	0	0
T48	0	32	0	0
T49	0	1	0	0
T50	0	14	0	0
T51	209754	0	0	0
T52	851103	0	0	0
T53	723811	0	0	0
T54	112398	0	0	0
T55	976583	0	0	0
T56	427062	0	0	0
T57	479286	0	0	0
T58	157454	0	0	0
T59	631661	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7048	0	0
T28	433892	1302	0	0
T43	0	699	0	0
T44	0	137	0	0
T45	0	1214	0	0
T46	0	2471	0	0
T47	0	5	0	0
T48	0	7	0	0
T49	0	3	0	0
T50	0	24	0	0
T51	209754	0	0	0
T52	851103	0	0	0
T53	723811	0	0	0
T54	112398	0	0	0
T55	976583	0	0	0
T56	427062	0	0	0
T57	479286	0	0	0
T58	157454	0	0	0
T59	631661	0	0	0
T60	0	29	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6116	0	0
T25	0	9	0	0
T28	433892	978	0	0
T43	0	625	0	0
T44	0	104	0	0
T45	0	1053	0	0
T46	0	2150	0	0
T47	0	8	0	0
T48	0	15	0	0
T49	0	4	0	0
T50	0	9	0	0
T51	209754	0	0	0
T52	851103	0	0	0
T53	723811	0	0	0
T54	112398	0	0	0
T55	976583	0	0	0
T56	427062	0	0	0
T57	479286	0	0	0
T58	157454	0	0	0
T59	631661	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6153	0	0
T25	0	6	0	0
T28	433892	1122	0	0
T43	0	479	0	0
T44	0	148	0	0
T45	0	1044	0	0
T46	0	2099	0	0
T47	0	10	0	0
T48	0	9	0	0
T49	0	9	0	0
T50	0	19	0	0
T51	209754	0	0	0
T52	851103	0	0	0
T53	723811	0	0	0
T54	112398	0	0	0
T55	976583	0	0	0
T56	427062	0	0	0
T57	479286	0	0	0
T58	157454	0	0	0
T59	631661	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8294	0	0
T11	475073	106	0	0
T12	631752	0	0	0
T13	422786	0	0	0
T27	202001	0	0	0
T28	0	1431	0	0
T35	155710	0	0	0
T36	260979	0	0	0
T37	862671	0	0	0
T38	167370	0	0	0
T39	187524	0	0	0
T40	286154	0	0	0
T57	0	24	0	0
T61	0	42	0	0
T62	0	51	0	0
T63	0	11	0	0
T64	0	28	0	0
T65	0	35	0	0
T66	0	33	0	0
T67	0	27	0	0